KR950005045B1 - High voltage converter with hot carrier protected circuit - Google Patents

Abstract

This converter reduces current transmission delay time by shortening a current path to transmit high voltage to load capacity and reduces a VPP current consumption. It comprises: (a) a voltage shifter(10) connected from a control input terminal and a charge pump; (b) a reverse gate G1 connected between a voltage shifter and a control input terminal; (c) a transistor Q5 having an output signal of the voltage shifter as a gate input; (d) a transistor H3 having VDD as a gate input; (e) a transistor Q6 having an output signal of the voltage shifter as a gate input; and (f) a hot-carrier protection circuit(H1),(H4) having a characteristic constructed as a load capacity connected between a connecting point of a transistor and GND.

Description

High Voltage Converter with Hot-Carrier Protection Circuit

1 is a circuit diagram of a typical high voltage converter.

2 is a waveform diagram for explaining the operation of FIG.

3 is a circuit diagram of a high voltage converter with a conventional hot-carrier protection circuit.

4 is a waveform diagram for explaining the operation of FIG.

5 is a circuit diagram of a high voltage converter with a hot-carrier protection circuit according to the present invention.

6 is a waveform diagram for explaining the operation of FIG.

* Explanation of symbols for main parts of the drawings

1 and 10: Voltage Shifter

Q1 to Q8: transistor

H1 to H4: Transistor for hot-carrier protection

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage converter having a hot-carrier protection circuit. In particular, the present invention relates to a high voltage converter having a hot-carrier protection circuit while reducing a current transfer delay time by shortening a current path for delivering a high voltage to a load capacity. It is about.

A circuit of a general high voltage converter is as shown in FIG. 1, the operation of which will be described with reference to FIG.

First, when the input voltage IN is VSS (logical "low" state), transistor Q3 is turned off while transistor Q4 is turned on. Therefore, the transistor Q2 remains off because the potential of the node B becomes "high" as the transistor Q1 is turned on because the potential of the node C becomes the "low" potential.

Transistor Q6 is turned off while transistor Q5 is turned on because the potential of node C remains at a "low" potential. According to the on operation of the transistor Q5, the transistor Q7 is turned off while the transistor Q8 is turned on so that the voltage charged in the load capacitance C _L is discharged through the transistor Q8.

When the input voltage IN is VDD (logical "high" state), transistor Q3 is on while transistor Q4 is off, so transistor Q1 is off and Q2 is on. Therefore, transistor Q5 is off while transistor Q6 is on. Eventually transistor Q8 is turned off and transistor Q7 is turned on so that high voltage VPP drives load capacitance C _L.

FIG. 3 is a circuit diagram of a high voltage converter having a conventional hot-carrier protection circuit for protecting the hot-carrier of the high voltage converter as shown in FIG. 1. The operation thereof will be described with reference to FIG.

The difference from FIG. 1 described above is that four transistors H1 to H4 having a VDD voltage as a gate input are provided to protect the hot-carrier. That is, since the VDD voltage is applied to the gate of the transistor H1 when the C node is VPP, the potential of the D node becomes VDD-V _TN (the threshold voltage of H1).

Since the voltage across the transistor H1 is VDD-V _TN , the potential of the D node is lower than the potential of the B node of FIG. 1 to prevent hot-carrier generation.

In addition, when driving the load capacitance C _L , first, the potential of the output terminal OUT is operated to VDD-V _TN (voltage between both ends of the transistor H4) using the current path through the inverting gate G3, and then the control input signal. According to the step by step driven by VPP, it is possible to reduce the consumption of the VPP current than to drive the load capacity to VPP at once as shown in FIG.

However, a circuit like FIG. 3 also has some disadvantages.

First, in order to drive C _L of the output to VDD-V _TN , it must go through transistors Q8 and H4 at inverted gate G3 and through transistors H4, Q8 and inverted gate G3 to send to VSS when C _L is VPP. It brings speed delay.

Second, even though the gate terminal potential of transistor Q8 of FIG. 3 is VPP, since the gate of transistor H4 is VDD, VDD of G3 cannot be sufficiently transferred and only VDD-V _TN (threshold voltage of NMOS) is not used to fully utilize VDD voltage. There is a disadvantage.

Therefore, the present invention reduces the current transfer delay time by shortening the current path for delivering high voltage to the load capacity, and reduces the consumption of VPP current and eliminates the above disadvantages by allowing the VDD voltage to be delivered to the load capacity without loss. The object is to provide a high voltage converter with a hot-carrier protection circuit.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 5 is a circuit diagram of a high voltage converter with a hot-carrier protection circuit according to the present invention. Referring to FIG.

In order to eliminate the speed delay caused by the addition of the hot-carrier protection transistor of the VPP driving stage shown in FIG.

That is, when G3 in FIG. 2 is separated into P1 and N2 in FIG. 5, and the OUT is driven to VDD, the transistor is reached through P1 and Q8 to reach OUT, and G3 to Q8 from G3 to Q8 as in FIG. One path can be reduced, and in FIG. 5, since the gate of Q8 is VPP, there is no voltage reduction as much as v _TN , so that VDD can be sufficiently delivered to the output node. That is, the consumption of the VPP current can be reduced by V _TN as compared with FIG. 3.

When discharging OUT from VPP to VSS (passage from N2 to N3) When the gate of N3 is VSS, first turn on the gate of N2 from VSS to VDD, turn node B to VDD-V _TN , and turn on N3 to VPP By keeping VPP, the highest voltage across N3 at VDD-V _TN , the hot-carrier protection and OUT to VSS path is also reduced by reducing one transistor from N2 to N3 rather than H4, Q8 and G3 as shown in FIG. You can increase the speed.

In summary, we remove H4 in Figure 3 to send OUT to VDD, take the paths of P1 and Q8 to reduce the number of transistors and eliminate V _TN losses to increase the speed and H4 in Figure 3 to send OUT from VPP to VSS. By removing and turning on N2 in FIG. 5 first, B node is made VDD-V _TN to achieve hot-carrier protection and speed up by reducing the number of transistors.

Referring to FIG. 6, in detail, first, when driving OUT to VPP, when IN goes from VSS to VDD, node C goes from VDD to VSS while P1 is 'on' and Q8 goes through OUT. Send from VSS to VDD.

When the signal through the voltage shifter 10 sends node A from VPP to VSS, the OUT already in VDD goes up to VPP.

Second, when sending OUT from VPP to VSS, IN goes from VDD to VSS, node C goes from VSS to VDD, node B sends from VSS to VDD from VDD to V _TN, and the voltage across N3 is below VDD-V _TN . When the signal, passed through the voltage shifter, raises node A from VSS to VPP, OUT is discharged from just two transistors N2, N3 from VPP to VSS.

As described above, according to the present invention, it is possible to shorten the current path for delivering the high voltage to the load capacity, thereby reducing the current transfer delay time and reducing the loss of the high voltage as much as possible.

Claims (1)

In the high voltage converter, a voltage shifter (10) connected from a charge pump and a control input terminal (IN) that generates VPP, an inverting gate (G1) connected between the voltage shifter (10) and a control input terminal (IN), and A transistor Q5 connected from the VPP of the voltage shifter 10 to the gate input of the output signal of the voltage shifter 10, a transistor H3 connected from the transistor Q5 to the gate input of VDD, and between the transistor H3 and ground. A transistor Q6 connected to the output signal of the voltage shifter 10 as a gate input, a transistor Q7 connected to a VPP of the voltage shifter 10 and a gate terminal connected to a connection point of the transistors Q5 and H3, and the transistor Q8, which is connected from Q7 and whose gate terminal is connected to the gate terminal of the transistor Q7, and an inverting probe connected from the control input terminal IN. Transistor G2, a transistor P1 connected between VDD and the transistor Q8 as a gate input, and an output signal of the inverted gate G2, and a transistor connected from a connection point of the transistors Q7 and Q8 and receiving the output signal of the inverted gate G2 as an input. A transistor N3 connected between the transistor N2 and ground, and a gate terminal connected to the gate terminal of the transistor Q8, and a load capacitance C _L connected between the connection point of the transistors Q7 and Q8 and ground. A high voltage converter with a hot-carrier protection circuit.