KR950004508A - Manufacturing method of plastic solid-state imaging device package - Google Patents
Manufacturing method of plastic solid-state imaging device package Download PDFInfo
- Publication number
- KR950004508A KR950004508A KR1019930014051A KR930014051A KR950004508A KR 950004508 A KR950004508 A KR 950004508A KR 1019930014051 A KR1019930014051 A KR 1019930014051A KR 930014051 A KR930014051 A KR 930014051A KR 950004508 A KR950004508 A KR 950004508A
- Authority
- KR
- South Korea
- Prior art keywords
- wall
- manufacturing
- plastic solid
- glass
- state image
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
본 발명은 플라스틱 고체촬상소자 패키지 제조방법에 관한 것으로, 생산성 향상을 기할수 있도록 하기위하여 웨이퍼 상태의 각 소자의 수광영역부 주위에 글래스리드 탑재를 위한 소정높이의 벽체를 마스크를 이용하여 일괄적으로 형성한후, 개개의 소자로 분리하는 소잉공정, 다이본딩 공정, 글래스리드 어태치 공정, 와이어본딩 공정, 몰딩 공정 및 트림/포밍 공정을 진행하는 것을 특징으로 하고 있다. 이와 같은 본 발명의 패키지 제조방법에 의하면, 웨이퍼 상태에서 각 소자의 수광영역부 주위에 글래스리드 탑재를 위한 벽체를 일괄적으로 형성함으로써 종래 소잉된 개개의 소자에 절연필름벽을 형성하는 기술에 비해 생산성을 현저하게 높일수 있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a plastic solid-state image pickup device package. In order to improve productivity, a wall having a predetermined height for mounting glass lid around the light receiving area of each device in a wafer state is collectively used using a mask. After the formation, the sawing process, the die bonding process, the glass lead attach process, the wire bonding process, the molding process, and the trimming / forming process are performed. According to the package manufacturing method of the present invention, the glass film mounting wall is collectively formed around the light-receiving area of each device in a wafer state, compared to the technique of forming an insulating film wall on individual elements that have been conventionally sawed. Productivity can be increased significantly.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명에 의한 플라스틱 고체촬상소자 패키지의 제조공정 플로우챠트.3 is a flowchart of a manufacturing process of a plastic solid-state image pickup device package according to the present invention.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930014051A KR960000707B1 (en) | 1993-07-23 | 1993-07-23 | Manufacturing method for package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930014051A KR960000707B1 (en) | 1993-07-23 | 1993-07-23 | Manufacturing method for package |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950004508A true KR950004508A (en) | 1995-02-18 |
KR960000707B1 KR960000707B1 (en) | 1996-01-11 |
Family
ID=19359922
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930014051A KR960000707B1 (en) | 1993-07-23 | 1993-07-23 | Manufacturing method for package |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960000707B1 (en) |
-
1993
- 1993-07-23 KR KR1019930014051A patent/KR960000707B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960000707B1 (en) | 1996-01-11 |
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Payment date: 20041230 Year of fee payment: 10 |
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