KR950004049A - Analog multiplier circuit - Google Patents

Analog multiplier circuit Download PDF

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Publication number
KR950004049A
KR950004049A KR1019940017027A KR19940017027A KR950004049A KR 950004049 A KR950004049 A KR 950004049A KR 1019940017027 A KR1019940017027 A KR 1019940017027A KR 19940017027 A KR19940017027 A KR 19940017027A KR 950004049 A KR950004049 A KR 950004049A
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South Korea
Prior art keywords
multiplier
output
buffering means
voltage
multiplication
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KR1019940017027A
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Korean (ko)
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KR960014199B1 (en
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김영환
하동석
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조백제
한국전기통신공사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/16—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division
    • G06G7/163—Arrangements for performing computing operations, e.g. operational amplifiers for multiplication or division using a variable impedance controlled by one of the input signals, variable amplification or transfer function

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)

Abstract

본 발명은 BiCMOS공정 또는 CMOS공정에서 만들어지는 바이폴라 트랜지스터와 CMOS FET, 그리고 GaAs FET를 이용하여 구현된 아날로그 곱셈기 회로에 관한 것으로서, 곱셈출력전압(V+ OUT, V- OUT)을 출력하도록 출력저항(ROUT)을 통해 양(＋) 공급전원(VDD)에 연결되면 입력전압을 버퍼링하기 위해 승수(피승수)의 신호값(V+ Y, V- Y)을 입력하는 버퍼링 수단과, 상기 버퍼링 수단에 드레인단이 각각 연결되고 게이트단으로는 피승수(피승수)의 신호값(V+ Y, V- Y)을 입력받아 곱셈연산을 수행하는 제1 내지 제4 NMOS FET(M1 내지 M4), 및 상기 제1내지 제4 NMOS FET(M1 내지 M4)에 연결되어 바이어스 전류를 제공하는 바이어스 전류원(IB)을 구비한 구성과, 또한, 상기 제1 내지 제4 NMOS FET(M1 내지 M4) 대신에 GaAs FET를 구비한 구성을 갖도록 하여, 전력소모가 적고, 칩으로 구현시 적은 면적으로 구현가능하며, 바이폴라 트랜지스터만을 이용한 종래의 곱셈기에 비해 입력전압의 범위가 매우 넓고 선형성이 좋아지며, 처리속도가 빠른 효과를 가진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog multiplier circuit implemented using a bipolar transistor, a CMOS FET, and a GaAs FET made in a BiCMOS process or a CMOS process, and outputs an output resistor (V + OUT , V - OUT ) to output a multiplication output voltage (V + OUT , V - OUT ). Buffering means for inputting a signal value (V + Y , V - Y ) of a multiplier (multiplier) to buffer an input voltage when connected to a positive supply voltage V DD through R OUT ) ; First to fourth NMOS FETs M1 to M4 connected to the drain terminals of the plurality of gate terminals, and multiplying the signal values V + Y and V - Y of the multiplicand (multiplier) to the gate end, and the And a bias current source I B connected to the first to fourth NMOS FETs M1 to M4 to provide a bias current, and also GaAs instead of the first to fourth NMOS FETs M1 to M4. It has a configuration with FET, so it consumes less power and is implemented in a chip It can be implemented in a small area, and the input voltage range is much wider, the linearity is better, and the processing speed is faster than a conventional multiplier using only bipolar transistors.

Description

아날로그 곱셈기 회로Analog multiplier circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 일실시예시도, 제4도는 본 발명의 다른 실시예시도.Figure 3 is an embodiment of the present invention, Figure 4 is another embodiment of the present invention.

Claims (6)

곱셈출력전압(V+ OUT, V- OUT)을 출력하도록 출력저항(ROUT)을 통해 양(＋) 공급전원(VDD)에 연결되면 입력전압을 버퍼링하기 위해 승수(피승수)의 신호값(V+ X, V- X)을 입력하는 버퍼링 수단과, 상기 버퍼링 수단에 드레인단이 각각 연결되어 버퍼링된 승수(피승수)의 신호값(V+ X, V- X)을 전달받고, 게이트단으로는 피승수(승수)의 신호값(V+ Y, V- Y)을 입력받아 곱셈연산을 수행하는 제1 내지 제4 NMOS FET(M1 내지 M4), 및 상기 제1내지 제4 NMOS FET(M1 내지 M4)의 각 소오스단에 공통으로 일단이 연결되고 타단은 음(－)공급전원(VSS)에 연결되어 바이어스 전류를 제공하는 바이어스 전류원 (IB)을 구비하는 것을 특징으로 하는 아날로그 곱셈기.Multiplying the output voltage (V + OUT, V - OUT) when the amount via an output resistor (R OUT) to output the (+) connected to a supply voltage (V DD) signal values of the multiplier (multiplicand) for buffering an input voltage ( Buffering means for inputting V + X , V - X , and a drain terminal is connected to the buffering means, respectively, to receive a signal value (V + X , V - X ) of a buffered multiplier (multiplier), and to the gate end. Is a first to fourth NMOS FETs (M1 to M4) and multiplies the signal values (V + Y , V - Y ) of the multipliers (multipliers), and the first to fourth NMOS FETs (M1 to M). And a bias current source (IB) having one end connected in common to each source end of M4) and the other end connected to a negative supply voltage (VSS) to provide a bias current. 제2항에 있어서, 상기 버퍼링 수단은, 승수(피승수) 신호값(V+ X, V- X)을 베이스단으로 입력받고 켈렉터단은 곱셈출력전압(V+ OUT, V- OUT)을 출력하도록 출력저항(ROUT)을 통해 양(＋) 공급전원(VDD)에 연결되고 에미터단은 곱셈연산을 수행하는 제1 내지 제4 NMOS FET(M1 내지 M4)의 각 드레인단에 연결되는 제1 내지 제4바이폴라 트랜지스터(Q1 내지 Q4)를구비하는 것을 특징으로 하는 아날로그 곱셈기.The method of claim 2, wherein the buffering means, the multiplier (multiplier) signal value (V + X , V - X ) is input to the base stage and the collector stage outputs a multiplication output voltage (V + OUT , V - OUT ) claim that is to be connected to the positive supply voltage (V DD) via an output resistor (R OUT), and the emitter teodan is connected to the first to the drain terminal of the 4 NMOS FET (M1 to M4) for performing a multiplication operation An analog multiplier comprising one to fourth bipolar transistors (Q1 to Q4). 제1항에 있어서, 상기 버퍼링 수단은, 승수(피승수) 신호값(V+ X, V- X)을 베이스단으로 입력받고 제1컬렉터단은 곱셈출력전압(V+ OUT, V- OUT)을 출력하도록 출력저항(ROUT)을 통해 양(＋) 공급전원(VDD)에 연결되고, 제2컬렉터단은 직접 양(＋) 공급전원(VDD)에 연결되고, 에미터단은 곱셈연산을 수행하는 제1 내지 제4 NMOS FET(M1 내지 M4)의 각 드레인단에 연결되는 제1 내지 제4기생 바이폴라 트랜지스터를 구비하는 것을 특징으로 하는 아날로그 곱셈기.The method of claim 1, wherein the buffering means, the multiplier (multiplier) signal value (V + X , V - X ) is input to the base stage and the first collector stage is a multiplication output voltage (V + OUT , V - OUT ) The output resistor R OUT is connected to the positive supply voltage V DD , the second collector stage is directly connected to the positive supply voltage VDD, and the emitter stage performs the multiplication operation. And first through fourth parasitic bipolar transistors connected to respective drain terminals of the first through fourth NMOS FETs (M1 through M4). 제1항에 있어서, 상기 버퍼링 수단은, 승수(피승수)신호값(V+ X, V- X)을 0.6 내지 0.7V레벨 쉬프트 시켜 제1내지 제4 NMOS FET(M1 내지 M4)의 각 드레인단으로 인가하도록 한 것을 특징으로 하는 아날로그 곱셈기.The draining device of claim 1, wherein the buffering means shifts the multiplier (multiplier) signal value (V + X , V - X ) by 0.6 to 0.7V level. Analog multiplier, characterized in that applied to. 곱셈출력전압(V+ OUT, V- OUT)을 출력하도록 출력저항(ROUT)을 통해 양(＋) 공급전원(VDD)에 연결되며 입력 전압을버퍼링하기 위해 승수(피승수)의 신호값(V+ X, V- X)을 입력하는 버퍼링 수단과, 상기 버퍼링수단에 드레인단이 각각 연결되어 버퍼링된 승수(피승수)의 신호값(V+ X, V- X)을 전달받고, 게이트단으로는 피승수(승수)의 신호값(V+ Y, V- Y)을 입력받아 곱셈연산을 수행하는 제1 내지 제4 GaAs FET(G1 내지 G4) 및 상기 제1 내지 제4 GaAs FET(G1 내지 G4)의 각 소오스단에 공통으로 일단이 연결되고 타단은 음(-)공급전원(VSS)에 연결되어 바이어스 전류를 제공하는 바이어스 전류원(IB)을 구비되는 것을 특징으로 하는 아날로그 곱셈기.Signal is positive through an output resistor (R OUT) to output a (+) power supply coupled to (V DD) and the multiplier (the multiplicand) for buffering an input voltage (- multiplying the output voltage (OUT V + OUT, V) Buffering means for inputting V + X , V - X , and a drain end is connected to the buffering means, respectively, to receive a signal value (V + X , V - X ) of the multiplier (multiplier) buffered, and to the gate end. Are first to fourth GaAs FETs (G1 to G4) and multiplication operations by receiving signal values (V + Y , V - Y ) of the multipliers (multipliers) and the first to fourth GaAs FETs (G1 to G4). And a bias current source (I B ) having one end connected in common to each source end of the N) and the other end connected to a negative supply (V SS ) to provide a bias current. 제5항에 있어서, 상기 버퍼링 수단은, 승수(피승수) 신호값(V+ X, V- X)을 게이트단으로 입력받고 드레인단은 곱셈출력전압(V+ OUT, V- OUT)을 출력하도록 출력저항(ROUT)을 통해 양(＋) 공급전원(VDD)에 연결되고 소오스단은 곱셈연산을 수행하는 제1 내지 제4 GaAs FET(G1내지 G4)의 각 드레인단에 연결되는 제5내지 제8 GaAs FET(G5 내지 G8)를 구비하는 것을 특징으로 하는 아날로그 곱셈기.The method of claim 5, wherein the buffering means, the multiplier (multiplier) signal value (V + X , V - X ) is input to the gate terminal and the drain stage to output the multiplication output voltage (V + OUT , V - OUT ). A fifth terminal connected to the positive supply voltage V DD through the output resistor R OUT , and a source terminal connected to each drain terminal of the first to fourth GaAs FETs G1 to G4 performing multiplication; And an eighth GaAs FET (G5 to G8). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940017027A 1993-07-28 1994-07-14 Analog multiplication circuits KR960014199B1 (en)

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KR930014487 1993-07-28
KR93-14487 1993-07-28

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100381784B1 (en) * 1996-04-22 2003-07-07 삼성탈레스 주식회사 Device for processing signal mixed with digital and analog data

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100615998B1 (en) * 2003-11-05 2006-08-28 주식회사 효성 Manufacturing method of transparent polyester container for excluding UV and the container manufactured by this method
US8559906B2 (en) * 2011-06-24 2013-10-15 Northrop Grumman Systems Corporation System and method for providing a carbon nanotube mixer

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* Cited by examiner, † Cited by third party
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JPH0632061B2 (en) * 1990-08-27 1994-04-27 喜光 松本 Analog multiplication / averaging circuit and power meter circuit using the circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100381784B1 (en) * 1996-04-22 2003-07-07 삼성탈레스 주식회사 Device for processing signal mixed with digital and analog data

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JP2685715B2 (en) 1997-12-03
KR960014199B1 (en) 1996-10-14
JPH0757026A (en) 1995-03-03

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