KR960014199B1 - Analog multiplication circuits - Google Patents

Abstract

The circuit is implemented by using a bipolar transistor, a CMOS transistor and a GaAs FET fabricated in the BiCMOS process or CMOS process. The circuit comprises: a buffering means inputting the signal value of the multiplier(multiplicand) to buffer an input voltage; a first or a forth NMOS FET(M1 or M4) performing the multiplication by receiving the signal value of the buffered multiplier(multiplicand) through the drain and the signal value of the buffered multiplicand(multiplier) through the gate; and a bias current source(IB) supplying the bias current.

Description

Analog multiplier circuit

1 is a conventional analog multiplier.

2a and 2b are graphs of voltage-current operating characteristics of NMOS and GaAs FETs, respectively.

3 is an embodiment of the present invention.

4 is another exemplary embodiment of the present invention.

5A through 5C are structural diagrams of parasitic bipolar transistors made in a pure COMS process.

6 is another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

ROUT: output resistance Q1 to Q4: first to fourth bipolar transistors

M1 to M4: first to fourth NMOS FETs, G1 to G8: first to eighth GaAs FETs IB: current source

The present invention relates to an analog multiplier circuit implemented using a bipolar transistor, a CMOS transistor, and a GaAs FET made in a BiCMOS process or a CMOS process.

Recently, with the development of large-scale integrated circuit technology, many complex circuits have been integrated into one chip. Especially, with the development of CMOS technology, signal processing chips having mixed digital and analog circuits have been produced. In the case of implementing a communication circuit or neural network circuit, a filter, and a voltage-gain control circuit, an analog circuit may enter, and an analog multiplier is required.

Until now, many analog multipliers implemented on integrated circuits have been proposed, and the design technology of the multiplier circuits has developed a lot, and circuits having various structures such as bipolar transistors and CMOS transistor circuits have been proposed.

In addition, research is being conducted on circuits having high speeds. Accordingly, much time and effort has been devoted to the development of high speed semiconductor devices. In particular, GaAs FET, which is a device that operates at high speed, has been developed, and high-speed operation circuits using this device have many applications in wireless communication, MMIC (Microwave Monolithic IC), and the like.

The structure of the conventional multiplier is generally an analog multiplier of Gibert cell structure proposed by Gibert. This structure uses a pure bipolar transistor, which has a drawback that the voltage range applied to the input side is very small, and it is difficult to use in a CMOS process because only a pure bipolar process is used, and there is a limitation in processing speed due to the use of a bipolar transistor.

Therefore, the present invention devised to solve the problems of the conventional multiplier is made of a single chip analog and digital functions, the power consumption is small, implemented in a small area in the chip, and has a high processing speed The purpose is to provide an analog multiplier.

The present invention to achieve the above object; Buffering means for inputting a signal value of a multiplier (multiplier) to output a multiply output voltage through an output resistor and buffering an input voltage, and a drain end connected to the buffering means for buffering A first to four NMOS FETs for receiving a multiplier signal value and a multiplicative operation by receiving a multiplier signal value for the second stage, and each source stage of the first to four NMOS FETs; Has a bias current source connected in common to one end and the other end connected to a negative supply to provide a bias current.

The buffering means is configured to receive a multiplier (multiplier) signal value at the base end, and the collector end is connected to a positive supply power through an output resistor, and the emitter end performs a multiplication operation. First to fourth bipolar transistors are connected to the respective drain terminals of the first to fourth NMOS FETs.

In addition, the buffering means, the multiplier (multiplier) signal value is input to the base stage and the first collector stage is connected to the positive supply power supply through the output resistor to output the multiplication output voltage, the second collector stage is directly The emitter stage may be provided with first to fourth bipolar transistors connected to positive supply power and connected to respective drain stages of the first to fourth NMOS FETs to perform multiplication operations.

In another embodiment, the present invention provides a buffering means connected to a positive supply power through an output resistor to output a multiply output voltage, and for inputting a multiplier (or multiplier) signal value to buffer the input voltage. A first to fourth GaAs having a drain terminal connected to the buffering means to receive a buffered multiplier (or multiplier) signal value, and a gate terminal to receive a multiplier (or multiplier) signal value and perform multiplication operation. A FET and a bias current source having one end connected in common to each source terminal of the first to fourth GaAs FETs, and the other end connected to a negative supply, may provide a bias current.

In another embodiment of the present invention, the buffering means receives a multiplier (multiplier) signal value at the gate terminal and the drain terminal is connected to a positive supply power through an output resistor to output a multiplication output voltage. The source terminal includes fifth to eighth GaAs FETs connected to respective drain terminals of the first to fourth GaAs FETs to perform multiplication operations.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A and 2B are graphs of voltage-current operating characteristics of NMOS FETs and GaAs FETs, respectively.

According to the present invention, the analog multiplier uses the input / output voltage-current characteristics of the NMOS FETs and the input / output voltage-current characteristics of the GaAs FETs, as shown in FIGS.

First, the operation characteristics of each NMOS FET and GaAs FET in the operation region are as follows.

First, in the blocking region, the voltage applied between the gate and the source is small. At this time, the current flowing between the drain and the source becomes zero.

Second, in the linear region, the voltage applied between the gate and the source is very small and the voltage applied between the drain and the source is very small. At this time, the current flowing between the drain and the source is applied to the voltage applied between the gate and the source and between the drain and the source. It depends, and acts like a voltage control resistor.

Third, in the saturation region, the voltage applied between the gate and the source is smaller than the voltage applied between the drain and the source, and the current flowing through the drain and source depends only on the voltage applied between the gate and the source.

And the voltage-current relationship and conditions in each operating region are as follows.

Blocking area

Condition: (V _GS -V _Tn ) 0

Current formula: I _DS = 0

Linear region

Condition: (V _GS -V _Tn ) V _DS

Current formula: I _DS = ((V _GS -V _Tn ) V _DS -1 / 2V ² _DS )

Saturation Zone

Condition: (V _GS -V _Tn ) V _DS

Current formula: I _DS = C (V _GS -V _Tn ) 2

Where I _DS = current flowing between drain and source

= Transmission conductance parameter

V _GS = Gate-source applied voltage

V _DS = Drain-source applied voltage

V _Tn = threshold voltage of the NMOS FET and GaAs FET.

The voltage-current relationship is shown as the relationship between V _GS and V _DS in FIGS. 2A and 2B.

The present invention utilizes operation in the linear region of each FET, and FIG. 3 shows the overall configuration of an analog multiplier according to an embodiment of the present invention.

According to an embodiment of the present invention, as shown in FIG. 3, an output resistor R _OUT connected to a positive supply power, bipolar transistors Q1 to Q4 for buffering an input voltage, and a multiplication operation NMOS FETs M1 to M4 and a bias current source I _B for supplying a bias current to the entire circuit. In the drawing, reference numerals V _DD , V _ss are positive and negative supply power, V ⁺ _X and V ^- _Y are multiplier (multiplier) input signals in multiplication, and V ⁺ _Y and V ^- _Y are multiplier (multiplier) input signals. , V ⁺ _OUT and V ^- _OUT represent output voltage signals, and V ₁ to V ₅ represent voltages at each node.

Normal operation of the embodiment according to the present invention configured as described above is as follows.

Supply power (V _DD , V _SS ) and bias current source (I Current flows through each of the bipolar transistors Q1 through Q4 and the NMOS FETs M1 through M4, and the multiplier (multiplier) signal voltage V _X (V ⁺ _X , V ^- _X ), which is the input voltage to the circuit. ) And the multiplicand (multiplier) signal voltages V _Y (V ⁺ _Y , V ^- _Y ) are applied, the bipolar transistors (Q1 to Q4) buffer the input voltage, where the emi of the bipolar transistors (Q1 to Q4) The terminator level shifts the multiplier (multiplier) signal voltage V ⁺ _X applied to the base to about 0.6 to 0.7 V, and this voltage is applied to the drain side of the NMOS FETs M1 to M4.

When the multiplicative (multiplier) signal voltages (V ⁺ _Y , V ^- _Y ) are applied to the gates of the NMOS FETs M1 to M4, and the in-phase signal of this signal is higher than the in-phase signal of the voltage applied to the drain, the NMOS FET M1 is applied. To M4), the operating region is placed in the linear region, and has the same characteristics as the voltage-controlled resistor as described above, and the output current at this time is approximately the input voltage of the gate (V ⁺ _Y , V ^- _Y). ) Is multiplied by the voltage applied to the drain to enable multiplication of the input signal.

As a result, the operation of the circuit also implements an analog multiplier using this principle, using four bipolar transistors (Q1 to Q4) and four NMOS FETs (M1 to M4). The bipolar transistors Q1 to Q4 are applied to the drain of the NMOS FET using a buffer and a level shift function, and the other input is applied to the gate of the NMOS FET, thereby implementing a multiplier having excellent linearity.

In addition, looking at the quantitative operation of an embodiment according to the present invention.

If the operating area of the NMOS FET is in the linear operating area, the relation between input voltage and output current is I _DS = ((V _GS -V _Tn ) V _DS -1 / 2V ² _DS ), and the current flowing between the drain and the source in the NMOS FET is expressed as a function of V _GS and V _DS and there is no V ² _DS component in the current relationship. In this case, I _DS is expressed as the product of V _GS and V _DS .

In FIG. 3, the signal of multiplier (multiplier) signal voltage V _X and multiplier (multiplier) signal voltage V _Y are full differential signals, and in the circuit structure, the signal of V _Y must have higher in phase signal component than V _X signal. In this case, each input signal is as follows.

V ⁺ _X =-V ⁺ _X = 1 / 2V _X

V ⁺ _Y = V ⁺ _Y + 1 / 2V _Y

V ⁺ _Y = V _Q ― 1 / 2V _Y

Where V _Q is the in-phase signal component of the V _Y signal and its voltage value is positive.

Looking at the voltage-current relations in the respective devices, first, the voltage between the base-emitter across the bipolar transistors Q1 to Q4 is expressed as follows.

V _BE = V _T IN (I _C / I _S ) where V _T = _K T / q I _C = collector current I _S = reverse saturation current. From the above equation, even though the current change of I _C is large, the change of V _BE is small. Therefore, assuming that the voltage change of V _BE of each bipolar transistor is very small, it is as follows.

V _BE = V _BE1 = V _BE2 = V _BE3 = V _BE4

Here, V _BE1 to V _BE4 represent the voltage between the base and the emitter of each bipolar transistor Q1 to Q4. therefore,

V ₁ = V ₂ = V ⁺ _X ―V _BE = 1 / 2V _X -V _BE

V ₃ = V ₄ = V ^- _X ―V _BE = ―1 / 2V _X -V _BE

, The current through each NMOS FET is displayed as

I _DS1 = ₁ ((V ^- _Y- V _TN ) (V ₁ -V ₅ ) -1/2 (V ₁ -V ₅ ) ² ]

I _DS2 = ₂ ((V ⁺ _Y- V _TN ) (V ₂ V ₅ ) -1/2 (V ₂ -V ₅ ) ² ]

I _DS3 = ₃ ((V ⁺ _Y- V _TN ) (V ₃ V ₅ ) -1/2 (V ₃ -V ₅ ) ² ]

I _DS4 = ₄ ((V ^- _Y- V _TN ) (V ₄ V ₅ ) -1/2 (V ₄ -V ₅ ) ² ]

The output voltage is

V _OUT = V ⁺ _OUT- V ^- _OUT = R _OUT1 (I _DS2 + I _DS4 )-R _OUT2 (I _DS1 + I _DS3 ).

If R _OUT1 = R _OUT2 = R _OUT3 and each NMOS FET has the same size ₁ = ₂ = ₃ = ₄ = Therefore, the output voltage is expressed as

V _OUT = R _OUT ((V ⁺ _Y- V ^- _Y ) (V _1- V ₅ )-(V ⁺ _Y- V ^- _Y ) (V _3- V ₅ )]

= R _OUT ((V ⁺ _Y- V ^- _Y ) (V ⁺ _X- V _VE- V ₅ )-(V ⁺ _Y- V ^- _Y ) (V ^- _X- V _VE- V ₅ )]

= R _OUT ((V ⁺ _Y- V ^- _Y ) (V ⁺ _X- V ^- _X ))

= R _OUT ((V _X V _Y )

From the above relation, the output voltage is expressed as the product of the input voltages V _X and V _Y as multipliers and multiplicands, and becomes an analog multiplier of 4 quadrant operation that operates regardless of the sign of V _X and V _Y. It also shows very linear characteristics.

The factor that determines the gain in the circuit It depends on the sign of and R _OUT , and it does not depend on V _Q or bias current I _B , supply voltage, etc. The greatest advantage of the embodiment according to the present invention as described above is that the input voltage range is very wide, and the linearity is good compared to the multiplier using only the bipolar transistor. In addition, when implemented in a small area in the bi-CMOS process has the advantage of low power consumption.

4 is a block diagram of an analog multiplier implemented using a bipolar transistor implemented in a pure CMOS process rather than a bi-MOS process.

As shown in the figure, the configuration according to another embodiment of the present invention is implemented by replacing the bipolar transistor in the configuration of the embodiment shown in Figure 3 with a bipolar transistor having two collectors, having two collectors The bipolar transistors are parasitic bipolar transistors in CMOS process technology. The configuration shown in FIG. 4 can be implemented by adding several processes to the general bi-CMOS process, and therefore may not be provided in the general CMOS process technology.

As a result, in another embodiment of the present invention, the parasitic bipolar transistor having two collectors is implemented to obtain the effect of the analog multiplier described in FIG.

5A to 5C are structural diagrams of the above-mentioned parasitic bipolar transistors made in a CMOS process. FIG. 5A is a vertical cross-sectional view, FIG. 5B is a horizontal cross-sectional view, and FIG. 5C is a symbol, and is made in a P-well process. This becomes the structure of the NPN transistor (if a N-well process, a PNP transistor is created).

The n-diffusion region in the P-well is a diffusion region of a source or a drain of an NMOS FET in a CMOS process, and the P-diffusion region is a substrate diffusion region for power contact of the P-well. diffusion). In addition, the N-diffusion region on the N-substrate becomes a substrate diffusion region for power contact, and the supply voltage source V _DD is always applied thereto.

In FIG. 5A, N-diff (1) and N-diff (2) are the emitter and the first collector of the bipolar transistor, the P-well is the base layer, and the channel length of the poly-silicon. length) becomes the thickness of the transistor base layer, and the bipolar transistor thus implemented is called a lateral bipolar transistor, and the collector here may have an arbitrary voltage.

However, this implementation creates another bipolar transistor between N-diff (1), P-well, and N-substrate. The collector's potential is always connected to V _DD . vertical) is called a transistor.

Therefore, when implementing a transistor in a CMOS process, a bipolar transistor having two collectors can be made, and one collector has a structure in which an arbitrary voltage value is always connected to one supply voltage source.

FIG. 5B shows a plan view of the layout when making a bipolar transistor in a CMOS process, and is shown in FIG. 5A as viewed vertically from the cutting plane A-A '.

5c shows a symbol of a bipolar transistor, in which the first collector represents a lateral transistor and the second collector represents a vertical transistor.

By implementing the circuit of FIG. 4 using the bipolar transistor described above, an analog multiplier that can operate linearly in a wide input voltage range can be made even using pure CMOS process technology.

6 shows a configuration of another embodiment according to the present invention, in which G1 to G8 represent GaAs FETs, respectively.

Another embodiment according to the present invention, as shown in the drawings, the GaAs FETs G1 to G4 for buffering the multiplier or multiplier signal voltage, and the multiplier input to the GaAs FETs G1 to G4 received the multiplier or multiplier signal voltage Or GaAs FETs G5 to G8 for multiplying the multiplicand signals and a bias current source I _B for providing a bias current to the entire circuit.

That is, another embodiment of the present invention is a bipolar transistor Q1 to Q4 and NMOS FETs M1 to M4 in the configuration of one embodiment and another embodiment of the present invention shown in Figures 3 and 4 as GaAs FET It has an alternative configuration.

Now, looking at the detailed operation description of another embodiment according to the present invention shown in Figure 6, the configuration shown in Figure 6 is the same as the configuration shown in Figure 3 qualitative operation and quantitative operation, Duplicate operation descriptions will be omitted, and only descriptions of differences will be described below.

When the operating region of the GaAs FETs G1 to G8 is in the linear operating region, the relation between the input voltage and the output constant voltage is

I _DS = _{[(V GS -V TN) (V} DS -1 / 2V) 2 DS ] When the current flowing between the drain and the source in the GaAs FET is V _GS and V _DS is represented by a function V _DS ² component in the relational expression of the If not present, I _DS is expressed as the product of V _GS and V _DS . In Fig. 6, the signals of the multiplier or multiplier signal voltages V _X and V _Y are full differential signals, and due to the circuit structure, the V _Y signal must have a higher signal component than the V _X signal, in which case each input signal Is as follows.

V ⁺ _X = -V ^- _X = 1 / 2V _X

V ⁺ _X = 1 / 2V _Y

V ^- _Y = -1 / 2V _Y

Herein, when G1 to G4 have a larger physical size than G5 to G8, G1 to G4 behave like buffers.

Therefore, the gate-source voltage of M1 to M4 maintains a substantially constant voltage regardless of the input signal voltage.

The current and output voltage flowing in each GaAs FET are the same as in the case of the NMOS FET in the configuration of FIG. 3, and in this fact, the output is the same as the configuration of the embodiment of the present invention shown in FIG. The voltage is expressed as the product of multiplier and multiplicative signal voltages V _X and V _Y , and it is an analog frequency mixer with four quadrants operating regardless of the sign of V _X and V _Y. Shows. Similarly, the factor that determines the gain in the circuit _{OUT Q B}

Claims (6)

Multiplying the output voltage (V ⁺ _OUT, V ^- _OUT) when the amount via an output resistor (R _OUT) to output the (+) connected to a supply voltage (V _DD) signal values of the multiplier (multiplicand) for buffering an input voltage ( Buffering means for inputting V ⁺ | _X , V ^- _X ), and a drain end is connected to the buffering means, respectively, to receive a signal value (V ⁺ _X , V ^- _X ) of a buffered multiplier (multiplier), First to fourth NMOS FETs (M1 to M4) and multiplication operation by receiving the signal value (V ⁺ _Y , V ^- _Y ) of the multiplier (multiplier), and the first to fourth NMOS FET (M1) And a bias current source (I _B ) having one end connected in common to each source end of M4) and the other end connected to a negative (−) power supply (V _SS ) to provide a bias current. The method of claim 2, wherein the buffering means, the multiplier (multiplier) signal value (V ⁺ _X , V ^- _X ) is input to the base stage and the selector stage is a multiplication output voltage (V ⁺ _OUT , V ^- _OUT ) It is connected to the positive supply voltage (V _DD ) through the output resistor (R _OUT ) to the output and the emitter stage is connected to each drain terminal of the first to fourth NMOS FETs (M1 to M4) performing the multiplication operation. An analog multiplier comprising first to fourth bipolar transistors (Q1 to Q4). The method of claim 1, wherein the buffering means, the multiplier (multiplier) signal value (V ⁺ _X , V ^- _X ) is input to the base stage and the first collector stage is a multiplication output voltage (V ⁺ _OUT , V ^- _OUT ) is connected to the positive supply voltage (V _DD) via an output resistor (R _OUT) to output, a second collector stage is connected directly to the positive supply voltage (V _DD), the emitter teodan is multiply operation And first through fourth parasitic bipolar transistors connected to respective drain terminals of the first through fourth NMOS FETs (M1 through M4). The drain of each of the first to fourth NMOS FETs (M1 to M4) according to claim 1, wherein the buffering means shifts the multiplier (multiplier) signal value (V ⁺ _X , V ^- _X ) by 0.6 to 0.7V level. An analog multiplier characterized in that applied to the stage. Signal is positive through an output resistor (R _OUT) to output a (+) power supply coupled to (V _DD) and the multiplier (the multiplicand) for buffering an input voltage ^(- multiplying the output voltage _(OUT V ⁺ _OUT, V) Buffering means for inputting V ⁺ | _X , V ^- _X ), and a drain terminal is connected to the buffering means, respectively, to receive a signal value (V ⁺ _X , V ^- _X ) of a buffered multiplier (multiplier), The first to fourth GaAs FETs (G1 to G4) and the first to fourth GaAs FETs (G1 to G4) that perform multiplication operations by receiving signal values (V ⁺ _Y , V ^- _Y ) of the multipliers. And a bias current source (I _B ) having one end connected in common to each source end of G4) and the other end connected to a negative supply (V _SS ) to provide a bias current. The method according to claim 5, wherein the pre-buffering means inputs a multiplier (multiplier) signal value (V ⁺ _X , V ^- _X ) to a gate terminal and the drain stage outputs a multiplication output voltage (V ⁺ _OUT , V ^- _OUT ). A fifth terminal connected to the positive supply voltage V _DD through the output resistor R _OUT , and a source terminal connected to each drain terminal of the first to fourth GaAs FETs G1 to G4 performing multiplication; And an eighth GaAs FET (G5 to G8).