KR950003388Y1 - Semiconductor memory circuit - Google Patents

Abstract

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Description

Semiconductor memory circuit

1 is a conventional SRAM structure diagram.

(A) to (d) of FIG. 2 are operation waveform diagrams for parts according to FIG.

3 is a semiconductor memory circuit diagram of the present invention.

(A)-(f) of FIG. 4 is an operation waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

1: column address buffer 2: low address buffer

3: column decoder 4: control unit

5: Memory Array 6: Low Decoder

7: Input buffer 8: Detection amplifier

9: output buffer 10: address latch control unit

11: column address latch part 12: low address latch part

10-1: delay unit T ₁ -T ₂ : transmission gate

I ₁ -I ₈ : Inverter NOR ₁ -NOR ₂ : Noah Gate

NAND ₁ : NANDGATE OR: OAGATE

MP ₁ : PMOS transistor MN ₁ : NMOS transistor

The present invention relates to a semiconductor memory circuit, and more particularly, to a semiconductor memory circuit suitable for preventing malfunction by eliminating ground bouning noise due to instantaneous overcurrent of the output buffer.

A first turn and a column address buffer (1) it is configured to receive an address (A _O -A _n) as shown In a conventional S-RAM structure diagram generating a column address to the buffer amplifier, an address (A _n -A _O) A low address buffer 2 that is buffered and amplified to generate a low address, a column decoder 3 that receives a column address of the column address buffer 1 and decodes it by a control signal of the controller 4, A memory array 5 that stores various data and outputs data which rises to the output signals of the column decoder 3 and the low address buffer 2, and the low address decoding by receiving the output data of the memory array 5; A low decoder 6, a sense amplifier 8 for sensing and amplifying the output signal of the low decoder 6, and an input buffer 7 for receiving and buffering the output signal of the row decoder 6; And exiting the sensing amplifier 8 An output buffer (9) for outputting a signal is received after the buffering and the ground of the common parts are electrically connected to each other. The output buffer unit 9 is applied to the output terminal of the sense amplifier 8 to the one input terminal of the NOR gate NOR through the inverter I ₁ and to the one input terminal of the NAND gate NAND ₁ . The output data enable signal (ODE) is applied to the other input terminal of the NOR gate NOR ₁ through the inverter I ₂ and to the other input terminal of the NAND gate NAND ₁ . The output signal of the gate NOR ₁ is applied to the PMOS transistor MP ₁ gate supplied with the power supply voltage V _DD as a source through the inverter I ₃ , and the NAND output signal is an inverter (NAND). I ₄₎ to be applied to the gate of the PMOS transistor (MP ₁₎ and the common drain connected NMOS transistor (MN ₁₎ by, a capacitor to the common drain connection point of the MOS transistors _{(MP 1), (MN 1} ) ( C ₁ ) is connected and configured.

An operation process and a problem of the conventional semiconductor memory circuit constructed as described above will be described with reference to FIG.

When the power supply voltage V _DD is applied and the address A _O -A _n is applied, the column address buffer 1 is buffered and amplified to generate a column address, which is applied to the column address decoder 3 and the low address server 2. ) Generates a low address in the same operation as the column address buffer and applies it to the memory array 5. At this time, the column address decoder 3 decodes the control signal of the control unit 4 and then applies it to the memory array 5. The memory array 5 stores the data corresponding to the column address and the row address selected as the block. The corresponding data is output to the low decoder 6, the low decoder 6 decodes the low address, and then the corresponding data is applied to the sense amplifier 8, and the corresponding data is input to the input buffer 7 ), The sense amplifier 8 amplifies the fine signal, applies it to the output buffer 9, buffers it, and outputs it. The input buffer 7 is buffered and then transmitted to the input address.

In this case, the output buffer 9 outputs a signal having a high potential state in which the sensing amplifier 8 is the same as in (a) of FIG. 2, and the output data enable (ODE) signal is the same as that in (b) in FIG. In this state, the inverters I ₃ and I ₄ output a low potential state to turn off the enMOS transistor MN ₁ and to conduct the PMOS transistor MP ₁₁ to conduct high potential equal to (c) of FIG. 2. When the sensing amplifier 8 outputs a low potential state at a high potential state as shown in (a) of FIG. 2, the noar gate NOR ₁ and the inverter I ₃ and The high potential signal through the NAND gate NAND ₁ and the inverter I ₄ is applied to the gates of the MOS transistors MP ₁ and MN ₁ .

As a result, the PMOS transistor MP ₁ is turned off and the NMOS transistor MN ₁ is turned on to output a low-potential signal. At this moment, a large amount of current flows through the NMOS transistor MN ₁ , resulting in ground bounce at the ground level, and thus electrically grounded to generate noise in the input address.

The conventional memory circuit operating as described above has a problem of degrading performance by affecting the input address due to the ground bounce phenomenon in which the ground level is increased when the output buffer is changed from the high potential state to the low potential state. have.

In view of the above problems, the present invention recognizes the timing of the ground bounce phenomenon and controls the latch of the input address at that time, and the input address at the time of ground bounce by the control signal of the address latch controller is fixed. By address latching the time latch to prevent noise, the performance of the entire system is improved to improve the performance.

3 is a semiconductor memory circuit diagram of the present invention, as shown therein, the column address buffer 1 and the low address buffer which are respectively generated as the column address and the low address by buffering and amplifying the input addresses A _O -A _n . 2) and the column decoder 3 which decodes the column address of the column address buffer 1 by the control signal of the controller 4, and the output signals of the column decoder 3 and the row decoder 2, respectively. The memory array 5 for outputting the corresponding data stored by the memory, the low decoder 6 for decoding the low block address among the output data of the memory array 5, and the corresponding data in the output of the low decoder 6; A sense amplifier 8 for amplifying a signal, an output buffer 9 for buffering an output signal of the sense amplifier 8, and an input buffer for buffering data not corresponding to an address among the outputs of the low decoder 6; (7) and the output burr An address latch control unit 10 for recognizing the ground bounce of (9) to control the input address latch, a column address latch unit 11 and a low address for latching the input address by the control signal of the address latch control unit 10; The latch unit 12 is configured, and the address latch control unit 10 is connected to an output terminal of the NAND gate NAND ₁ of the output buffer 9 and an input terminal of the NOR gate NOR ₂ and a delay unit ( 10-1) and the inverter I ₅ are connected to the other input terminal, and the output terminal of the NOA gate (NOR ₂ ) is connected to the OR gate (OR ₁ ) multi-stage input terminal (IN ₁ -IN _n ). the column address latch section 11 is the address latch control section 10 Iowa gate output terminal a control terminal (g ₁₎ and a transfer gate of the transfer gate (T ₁₎ of the (OR ₁₎ (T _2), a control terminal (g ) And the output terminal of the transfer gate T ₁ through the inverter I _{8 is} connected to the inverter I ₇ ) is connected to the column address buffer 1 through the inverter (I ₈ ) and the transfer gate (T ₂ ) through the output terminal of the transfer gate (T ₁ ) and the low address latch portion 12 The parts are configured in the same manner and the parts are electrically common grounded.

The operation process and the effect of the present invention constructed as described above will be described with reference to FIG.

The column address and the low address are generated in the column address buffer 1 and the low address buffer 2, and the data of the memory array 5 is decoded by the column decoder 3 and the low decoder 6 to input / output buffers 7. Buffering at (9) and (9) is the same as in the prior art, and the operation of the output buffer 9 is performed at the low potential while the sensing amplifier 8 outputs a high-potential signal in the same manner as in (a) of FIG. When the output signal is enabled and the output data enable signal (ODE) is in the high potential state, the PMOS transistor MP ₁ is turned off and the NMOS transistor MN ₁ is turned on to output the low potential signal.

At this time, due to the momentary large current, ground bounce occurs in which the ground level rises instantaneously as in FIG. 4 (b).

In this case, the output signal of the sensing amplifier 8 is changed from the high potential state to the low potential state so that the NAND gate NAND ₁ of the output buffer 9 receives the high-potential state signal as shown in FIG. When the signal is output in the low potential state, the delay unit 10-1 of the address latch control unit 10 delays the predetermined time and outputs the same waveform as in FIG. 4D through the inverter I ₅ .

At this time, the OR gate OR ₁ rings the signals of the respective input terminals IN1-IN _n and then controls the column address latch 11 and the transfer gate T _{1 in the} same waveform as in FIG. 4 (f). Control terminal via inverter I ₇ with high-potential signal at terminal g ₁ A low potential signal is applied to the signal to turn off the transfer gate T ₁ to stop the input address and to control the control terminal of the transfer gate T ₂ . , (g ₂ ) by applying a low potential signal and a high potential signal through the inverter (I ₈ ), respectively, and conducts the transfer gate (T ₂ ) to the existing through the inverter (I ₇ ), (I ₈ ) The address is applied to the column address buffer 1 and the low address latch unit 12 also performs the same operation as the column address latch unit 11.

Then, when the output signal of the sense amplifier 8 changes to a high potential state, the address latch control unit 10 recognizes this and then controls the column address latch unit 11 and the low address latch unit 12 in FIG. Enter a normal address as in (e).

The semiconductor memory circuit of the present invention described in detail above recognizes a state in which an input address malfunctions due to ground bounce due to an instantaneous large current flow in the output buffer and latches the input address when the ground bounce occurs. It is effective to prevent malfunction and improve the performance and reliability of the device.

Claims (3)

A column that receives an address and buffers a column address and a row address, a row address buffer (1) and (2), and a column decoder (3) which decodes the column address and selects data of the memory array (5); A low decoder 6 for decoding the block data of the memory array 5, and an input / output buffer 7 for buffering the data of the low decoder 6 and the data of the sense amplifier 8; In the SRAM configured of (1), the address latch control unit (10) for controlling the input address by recognizing the ground bounce of the output buffer (9) and the column and low address by the control signal of the address latch control unit (10). 10. A semiconductor memory circuit comprising a column for latching a latch and a row address latch section (11). The semiconductor device according to claim 1, wherein the address latch control unit (10) is configured to delay and invert the signal of the output buffer (9) and the signal for a predetermined time, to invert the signal, and to output the ring signal with the respective signals. Memory circuit. The column address latch 11 and the low address latch 12 are transfer gates T ₁ , T (T ₁ ) and (T) to which an address A _O -A _n is applied as an output terminal of the address latch control unit 10. ₂ ) control terminal (g ₂ ) and the control terminals (g ₁ ) of the transmission gates (T ₁ ) and (T ₂ ) through the inverter (I ₈ ), respectively. Is connected to, the transfer gate (T ₁₎ is an inverter _{(I 7), (I 8} ) and the inverter (I ₈₎ is connected to the output terminal, the transfer gates transfer gate (T ₁₎ through (T ₂₎ Is a semiconductor memory circuit constructed by being connected to a column address buffer 1 and a low address buffer 2;