KR950001861A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR950001861A
KR950001861A KR1019940010935A KR19940010935A KR950001861A KR 950001861 A KR950001861 A KR 950001861A KR 1019940010935 A KR1019940010935 A KR 1019940010935A KR 19940010935 A KR19940010935 A KR 19940010935A KR 950001861 A KR950001861 A KR 950001861A
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KR
South Korea
Prior art keywords
insulating film
wiring layer
manufacturing
semiconductor device
cvd method
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KR1019940010935A
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Korean (ko)
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KR0149468B1 (en
Inventor
쭈까사 도이
Original Assignee
쓰지 하루오
샤프 가부시끼가이샤
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Application filed by 쓰지 하루오, 샤프 가부시끼가이샤 filed Critical 쓰지 하루오
Publication of KR950001861A publication Critical patent/KR950001861A/en
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Publication of KR0149468B1 publication Critical patent/KR0149468B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 기판위에 하부 배선층을 형성하는 공정과, 상기 하부 배선층을 전체적으로 피복할 수 있도록 소스로서 질소를 포함하는 유기실리콘 화합물을 사용하는 플라즈마 CVD방법에 의해 상기 하부 배선층 상부에 제 1 절연막을 형성하는 공정과, TEOS-O3계를 사용한 상압 CVD방법에 의해 상기 제 1 절연막 상부에 제 2 절연막을 형성하는 공정과, 이어서 유기 실라놀 글래스를 코팅한 후 열처리하여 경화시키는 공정과, 상기 제 2 절연막을 에치-백 시킨 후 플라즈마 CVD방법에 의해 평활화 된 제 3 절연막을 형성하는 공정으로 이루어진다. 본 발명에 의하면, TEOS-O3계를 사용한 상압 CVD방법에 의해 수분함량이 적고 고밀도의 절연막을 형성할 수 있다.The present invention provides a method of forming a first insulating film on an upper portion of a lower wiring layer by a process of forming a lower wiring layer on a substrate and a plasma CVD method using an organosilicon compound containing nitrogen as a source to cover the lower wiring layer as a whole. Forming a second insulating film on the first insulating film by an atmospheric pressure CVD method using a TEOS-O 3 system, followed by coating and organizing an organic silanol glass, followed by heat treatment to cure the second insulating film After etch-back is formed to form a third insulating film smoothed by the plasma CVD method. According to the present invention, an insulating film having a low moisture content and a high density can be formed by an atmospheric pressure CVD method using a TEOS-O 3 system.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명의 일실시예에 의한 반도체 장치의 제조방법을 설명하는 도면.1 is a view for explaining a method of manufacturing a semiconductor device according to one embodiment of the present invention.

Claims (5)

소스(source)로서 질소를 함유한 유기실리콘 화합물을 사용한 플라즈마 CVD방법에 의해 반도체 기판의 전표면을 피복하도록 배선층을 갖는 반도체 기판 위에 제 1 절연막을 증착하는 공정과, TEOS-O3계를 사용한 상압 CVD방법에 의해 상기 제 1 절연막의 표면을 피복하도록 제 2 절연막을 증착하는 공정으로 이루어지는 것을 특징으로 하는 반도체 장치의 제조방법.A process of depositing a first insulating film on a semiconductor substrate having a wiring layer so as to cover the entire surface of the semiconductor substrate by a plasma CVD method using an organosilicon compound containing nitrogen as a source, and an atmospheric pressure using a TEOS-O 3 system And depositing a second insulating film so as to cover the surface of said first insulating film by a CVD method. 제 1 항에 있어서, 상기 질소를 포함하는 유기실리콘 화합물은 헥사메틸디실라젠, N, 0-비스(트리메틸실릴)아세토아미드, 헵타메틸디실라젠, 1,1,3,3,5,5,7,7-옥타메틸사이클로테트라실라젠 및 디에틸아미노트리메틸실란으로 이루어진 그룹 가운데 어느 하나로 이루어진 것을 특징으로 하는 반도체 장치의 제조방법.The method of claim 1, wherein the organosilicon compound containing nitrogen is hexamethyldisilagen, N, 0-bis (trimethylsilyl) acetoamide, heptamethyldisilagen, 1,1,3,3,5,5 A method for manufacturing a semiconductor device, comprising any one of a group consisting of 7,7-octamethylcyclotetrasilazene and diethylaminotrimethylsilane. 제 1 항에 있어서, 상부 배선층이 상기 제 2 절연막 위에 형성되는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein an upper wiring layer is formed on said second insulating film. 제 3 항에 있어서, 상기 제 2 절연막을 에치-백한 후 플라즈마 CVD방법에 의해 제 3 절연막을 형성하는 공정과, 상기 제 1 절연막의 하부에 제공된 하부 배선층과 상기 제 3 절연막 위의 상부 배선층을 관통홀을 통하여 접속시키는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.4. The method of claim 3, further comprising: forming a third insulating film by etching the second insulating film after plasma etching, and passing through the lower wiring layer provided below the first insulating film and the upper wiring layer above the third insulating film. A method of manufacturing a semiconductor device, comprising the step of connecting through a hole. 제 4 항에 있어서, 플러그가 상기 관통홀에 형성되어 상기 상부 배선층과 상기 하부 배선층을 접속시키는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein a plug is formed in said through hole to connect said upper wiring layer and said lower wiring layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940010935A 1993-06-16 1994-05-19 A method for forming a semiconductor device KR0149468B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-144751 1993-06-16
JP5144751A JP2981366B2 (en) 1993-06-16 1993-06-16 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
KR950001861A true KR950001861A (en) 1995-01-04
KR0149468B1 KR0149468B1 (en) 1998-12-01

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KR (1) KR0149468B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100230365B1 (en) * 1996-06-29 1999-11-15 윤종용 Method for interlayer insulation film formatiom of semiconductor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419878B1 (en) * 1997-12-11 2004-05-20 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100659394B1 (en) 2005-08-08 2006-12-19 삼성전자주식회사 Method of forming an insulation layer and method of manufacturing a semiconductor device by using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100230365B1 (en) * 1996-06-29 1999-11-15 윤종용 Method for interlayer insulation film formatiom of semiconductor

Also Published As

Publication number Publication date
JPH0714917A (en) 1995-01-17
JP2981366B2 (en) 1999-11-22
KR0149468B1 (en) 1998-12-01

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