KR950000436B1 - Voltage generator - Google Patents

Abstract

The generator comprises a first and a second input ports (301,302) for inputting external power, a first and a second output ports (303,304) for outputting polarity-adjusted port voltage, a first and a second switch for switching between the second output port and input ports according to a signal of the first and the second input ports (301,302) to always keep low level in the second output port at a time, and a third and a forth switch for switching between the first output port and input port according to a signal of first and a second input port (301,302) to always keep high level in the first output port at a time.

Description

Terminal voltage generator

1 shows a relationship between a conventional power supply and an electronic device.

2 shows a relationship between a conventional power supply and a semiconductor IC.

3a to 3d are circuit diagrams of a terminal voltage generator according to the present invention.

4 is a diagram showing a power supply in a semiconductor IC incorporating a terminal voltage generator.

5 is a diagram showing a power supply in an electronic device to which a terminal voltage generator is attached.

The present invention relates to a terminal voltage generator for supplying power without discriminating polarity.

In case of power supply by using battery or adapter in general electronic products, power voltage must be connected with + polarity and-polarity. However, when the battery is inserted or the adapter is connected, the polarity may be reversed. In such a case, excessive current flows to the electronic product, and thus the battery is easily consumed. Cause The adapter may be damaged. In addition, when the electronic product is a logic circuit, there is a problem of performing a malfunction.

1 shows a relationship between a conventional power supply and an electronic device.

In FIG. 1, the electronic product 103 is composed of a semiconductor IC 101 and a diode DI, and the power supply supplies a "low" level voltage (hereinafter referred to as "below voltage") to the Vcc stage. When a voltage of "high" level (hereinafter referred to as + voltage) is supplied to the G _ND terminal, the diode (DI) is biased in the forward direction so that an excessive current flows and an excessive current flows in the semiconductor IC 101, resulting in large current consumption and damage to components. Will be.

2 shows a relationship between a conventional power supply and a semiconductor IC.

In FIG. 2, when the power is applied to the semiconductor IC internal circuit with the opposite polarity, the diodes D2, D3, and D4 are forward biased so that excessive current flows and the semiconductor circuit is damaged by heat.

Therefore, an object of the present invention is to control the polarity of the terminal even if the power supply is connected without distinction between + and-polarities and applied to an electronic device or a semiconductor circuit to prevent damage and malfunction of an electronic product or a semiconductor circuit. It is to provide a generator.

In order to achieve the above object, the terminal voltage generator of the present invention inputs a direct current (DC) power source from the outside without discriminating polarity, and in the apparatus for supplying power of an electronic device, the first input terminal for inputting the external power source And a second input terminal; A first output terminal and a second output terminal for outputting a terminal voltage whose polarity is adjusted; Each switch is switched according to a signal of the first input terminal and the second input terminal, and is connected to the second output terminal in common with each other. At any one time, any one of them is turned on so that the second output terminal always has a "low" level. First and second switching means for indicating; Are switched according to the signals of the first input terminal and the second input terminal, and are connected to the first output terminal in common with each other, and at any one time, any one of them is turned on so that the first output terminal always has a high level. And a third switching means and a fourth switching means, wherein the first input terminal and the second input terminal are freely connected to each other without polarity.

Next, the terminal voltage generator of the present invention will be described in more detail with reference to FIGS. 3 to 5.

3A to 3D use MOS transistors as switching means as circuit diagrams according to an embodiment of the terminal voltage generator according to the present invention. The switching means may use other switching elements in addition to the MOS transistor, but it is advantageous to configure the MOS transistor in an integrated circuit (IC).

3A illustrates the first embodiment, in which the first input terminal 301, the second input terminal 302, the first output terminal 303 (Vcc ′) and the second output terminal 304 (G _ND ′) are illustrated. And NMOS transistors NM2 and NM3, PMOS transistors PM2 and PM3, diodes D5, D6, D7, D8 and D9, resistors R1 and R2, and the like.

In FIG. 3A, an external power source is applied to the first input terminal 301 and the second input terminal 302. The polarity of the external power source may be +,-, or-, +.

The first output terminal 303 (Vcc ') and the second output terminal 304 (G _ND ') are portions for outputting a terminal voltage whose polarity is adjusted.

NMOS transistors NM2 and NM3 are connected to the first input terminal 301 and the second input terminal 302, and a drain is connected to each other, and the source is commonly connected to the second output terminal. Each gate is connected to the second input terminal and the first input terminal through resistors R1 and R2, respectively, as opposed to the drain, so that the first input terminal 301 and the second input terminal ( The switching operation according to the signal applied to 302 is performed. The signals applied to the first input terminal 301 and the second input terminal 302 always have polarities opposite to each other at any point in time, so any one of the two NMOS transistors NM2 and NM3 is conductive. Switching ON) and the other is Switching OFF. For example, referring to a case in which a positive polarity voltage is applied to the first input terminal 301 and a negative polarity voltage is applied to the second input terminal 302, NM3, which is an NMOS transistor, is formed of the first input terminal 301. The signal is turned on because it is applied through the resistor R1, and the NMOS transistor NM2 is blocked because the signal of the second input terminal 302 is applied through the resistor R2. Therefore, the voltage level of the second output terminal 304 (G _ND ′) becomes the "low" level, i.e., polarity. On the contrary, when a positive polarity voltage is applied to the second input terminal 302 and a negative polarity voltage is applied to the first input terminal 301, the NMOS transistor NM2 is applied with a positive polarity voltage of "high" level. And the NMOS transistor NM3 is cut off because a -polar voltage of "low" level is applied, so that the voltage level of the second output terminal 304 (G _ND ') is -polar.

PMOS transistors PM2 and PM3 have a drain connected to the first input terminal 301 and the second input terminal 302, respectively, and a source connected to each other, so that the first output terminal 303 (Vcc) Is connected to '). Each gate is connected to the second input terminal and the first input terminal through resistors R1 and R2, respectively, as opposed to the drain, so that the first input terminal 301 and the second input terminal ( The switching operation according to the signal applied to 302 is performed. Here, the PMOS transistor is a switching device having duality with the NMOS transistor. The PMOS transistor has a "high" level at the first output terminal 303 (Vcc '), unlike the second output terminal 304 (G _ND '). The polarity voltage level is displayed. That is, similarly to the pair of NMOS transistors NM2 and NM3, any one of the two conductive PMOS transistors is turned on at any time and the other is blocked, and the voltage level applied to the drain of the PMOS transistor, which is conducted between the two PMOS transistors, is applied to the first output terminal 303. ; Vcc '), the voltage level of the first output terminal 303 (Vcc') is always at the "high" level (+ polarity).

In FIG. 3A, the diode D5 is connected in a reverse direction between the first input terminal 301 and the second output terminal 304 (G _ND ′), and the diode D6 is connected to the second input terminal 302. The second output terminal 304 (G _ND ') is connected in the reverse direction, the two diodes (D5, D6) are connected to each other anode, if the voltage level of the second output terminal 304 (G _ND ') When the voltage level of the first input terminal 301 and the second input terminal 302 is higher than the voltage level of the first input terminal 301 and the second input terminal 302, the voltage level of the second output terminal 304 (G _ND ') is set to the "low" level.

Similarly, the diode D7 is connected in a forward direction between the first input terminal 301 and the first output terminal 303 (Vcc '), and the diode D8 is connected to the second input terminal 302 and the first output terminal 303; Vcc ') is connected in the forward direction and the two diodes D7 and D8 are connected to the cathode. If the voltage level of the first output terminal 303 (Vcc') is equal to the first input terminal 301 and the first, When lower than the voltage level of the second input terminal 302, current flows in the forward direction, thereby maintaining the voltage level of the first output terminal 303 (Vcc ') at a "high" level. The diode D9 causes the current to flow in the forward direction when the voltage level of the second output terminal 304 (G _ND ′) is higher than the first output terminal 303 (Vcc ') and thus the first output terminal 303 (Vcc') and The polarity of the second output terminal 304 (G _ND ′) is not reversed.

In FIG. 3A, the resistors R1 and R2 serve to prevent a direct power supply voltage from being applied to the PMOS transistors and the NMOS transistor gates, thereby protecting the gate portion. NMOS transistors and PMOS transistors should be made sufficiently low in resistance to conduct so that they can supply a large amount of current when conducting. In order to ensure that the diodes performing additional functions are always reverse biased, the bulk of the NMOS transistors NM2 and NM3 is applied to the terminal ② and the bulk of the PMOS transistors PM2 and PM3 is applied to the terminal ①. Do it.

3b shows a second embodiment of the terminal voltage generator according to the present invention, wherein the first input terminal 301 and the second input terminal 302, the first output terminal 303 (Vcc ') and the second output terminal ( 304; G _ND '), NMOS transistors NM4, NM5, PMOS transistors PM4, PM5, diodes D5, D6, D7, D8, D9, resistors R3, R4, and the like.

3B is configured due to the duality of the PMOS transistor and the NMOS transistor in comparison with the configuration of FIG. 3A. The PMOS transistors PM4 and PM5 are configured instead of the NMOS transistors NM2 and NM3. Voltages applied to the electric fields are reversely connected to those in FIG. 3a. That is, the signal of the first input terminal 301 is applied to the PMOS transistor PM4, and the signal of the second input terminal 302 is applied to the PMOS transistor PM5. Even in such a configuration, the second output terminal 304 (G _ND ′) is always connected to any one of the two PMOS transistors PM4 and PM5 so that it is always " low " Meanwhile, the NMOS transistors NM4 and NM5 connected to the first output terminal 303 (Vcc ') are also connected in place of the PMOS transistors PM2 and PM3 of FIG. 3A. In this case, the voltage applied to the gate is opposite to that of FIG. 3A. To be connected. Therefore, the voltage level at the first output terminal 303 (Vcc ') is always at a "high" level (+ polarity) by turning off either of the NMOS transistors NM4 and NM5 and the other.

Diodes D5, D6, D7, D8, and D9 of FIG. 3B also perform the same functions as in FIG. 3A.

3c shows a third embodiment of the terminal voltage generator according to the present invention, wherein the first input terminal 301 and the second input terminal 302, the first output terminal 303 (Vcc ') and the second output terminal ( 304; G _ND ') and NMOS transistors NM6, NM7, NM8, NM9 diodes D5, D6, D7, D8, D9, resistors R3, R4, and the like.

In FIG. 3C, the PMOS transistors PM2 and PM3 connected to the first output terminal 303 (Vcc ') are composed of NMOS transistors NM8 and NM9 having duality therebetween, and the gate is configured. The first input terminal 301 and the second input terminal 302 are respectively connected. The operation is the same as in FIG. 3b for the first output terminal 303 (Vcc ') and in FIG. 3a for the second output terminal 304 (G _ND '). The diodes do the same.

3d illustrates a fourth embodiment of the terminal voltage generator according to the present invention, in which a first input terminal 301, a second input terminal 302, a first output terminal 303 (Vcc ') and a second output terminal ( 304; G _ND '), PMOS transistors PM6, PM7, PM8, PM9, diodes D5, D6, D7, D8, D9, resistors R3, R4, and the like.

In FIG. 3D, the NMOS transistors NM2 and NM3 connected to the second output terminal 304 (G _ND ') in the configuration of FIG. 3A are composed of PMOS transistors PM6 and PM7 having duality therebetween, and the gate is configured. The first input terminal 301 and the second input terminal 302 are respectively connected. The operation is the same as in FIG. 3A for the first output terminal 303 (Vcc ') and in FIG. 3B for the second output terminal 304 (G _ND '). The diodes do the same.

The terminal voltage generator performing the above function may be configured with other switching elements than the present embodiments.

4 is a diagram showing power supply from a semiconductor IC 401 incorporating a terminal voltage generator. In the fabrication of an IC function circuit 403 composed of a semiconductor process, the terminal voltage generator 402 having the above configuration is shown. Can be manufactured in a built-in form between the terminal to which the power is supplied and the IC function circuit 403.

5 is a diagram showing a power supply in an electronic device to which a terminal voltage generator is attached. That is, as an example of applying the terminal voltage generator 402 according to the present invention to a set of electronic products, the capacitor C has a large amount of current flowing during the operation of the IC functional circuit unit 501 so that the voltage Vcc 'or G _ND ' varies somewhat. In addition, it performs a function to make the change less or no.

As described above, the present invention is a device that connects without discriminating the polarity of the power source and compensates it internally, which increases the user's convenience and may cause damage or malfunction of the electronic device that may appear when the polarity of the power source is incorrectly connected. It is effective to prevent.

Claims (10)

An apparatus for supplying power of an electronic device by inputting DC power from outside without distinguishing polarity, the apparatus comprising: a first input terminal and a second input terminal for inputting the external power; A first output terminal and a second output terminal for outputting a terminal voltage whose polarity is adjusted; Each switch is switched according to a signal of the first input terminal and the second input terminal, and is connected to the second output terminal in common with each other. At any one time, any one of them is turned on so that the second output terminal always has a "low" level. First and second switching means for indicating; Are switched according to the signals of the first input terminal and the second input terminal, and are connected to the first output terminal in common with each other, and at any time, any one of them is turned on so that the first output terminal always has a "high" level. And a third switching means and a fourth switching means, wherein the first input terminal and the second input terminal freely connect the power source without discriminating polarity. The method of claim 1, wherein the first switching means, the second switching means, the third switching means and the fourth switching means are respectively composed of a first transistor, a second transistor, a third transistor and a fourth transistor. Terminal voltage generator. The method of claim 2, wherein a first diode (D5) is connected in the reverse direction between the first input terminal and the second output terminal, the second diode (D6) in the reverse direction between the second input terminal and the second output terminal. And the voltage level displayed at the second output terminal is always lower than the voltage level displayed at the first input terminal and the second input terminal. 3. The method of claim 2, wherein a third diode (D7) is connected in the forward direction between the first input terminal and the first output terminal, the fourth diode (D8) in the forward direction between the second input terminal and the first output terminal. And the voltage level displayed at the first output terminal is always higher than the voltage level displayed at the first input terminal and the second input terminal. The method of claim 2, wherein the fifth diode (D9) is connected between the first output terminal and the second output terminal in the forward direction so that the level of the first output terminal is higher than the level of the second output terminal. Terminal voltage generator. 3. The terminal voltage generator of claim 2, wherein the terminal voltage generator is embedded in a semiconductor IC. The drain and drain terminals of the first transistor and the second transistor are connected to the first input terminal and the second input terminal, respectively, and the source is commonly connected to the second output terminal. The gate is connected to the second input terminal and the first input terminal through resistors R1 and R2, respectively, as opposed to the drain, so that any one of the gates is turned on at any time and the second output. A first NMOS transistor NM2 and a second NMO transistor NM3 having the terminal's voltage level "low"; A drain is connected to the first input terminal and a second input terminal of the third transistor and the fourth transistor, respectively, and a source is commonly connected to the first output terminal. Is connected to the second input terminal and the first input terminal through the resistors R1 and R2, respectively, so that any one of the conduction is conducted at any point in time, thereby reducing the voltage level of the first output terminal. And a second PMOS transistor (PM2) and a second PMOS transistor (PM3). The drain and drain terminals of the first transistor and the second transistor are connected to the first input terminal and the second input terminal, respectively, and the source is commonly connected to the second output terminal. The gate is connected to the first input terminal and the second input terminal through resistors R3 and R4, respectively, as opposed to the drain, so that any one of the gates is turned on at any time and the second output is connected. A first PMOS transistor PM4 and a second PMOS transistor PM5 having the terminal's voltage level "low"; A drain is connected to the first input terminal and a second input terminal of the third transistor and the fourth transistor, respectively, and a source is commonly connected to the first output terminal. ) Is connected to the first input terminal and the second input terminal through the resistors R3 and R4, respectively, in contrast to the drain, so that any one of the conduction is conducted at any time, thereby reducing the voltage level of the first output terminal. And a second NMOS transistor (NM4) and a second NMOS transistor (NM5). The drain and drain terminals of the first transistor and the second transistor are connected to the first input terminal and the second input terminal, respectively, and the source is commonly connected to the second output terminal. The gate is connected to the second input terminal and the first input terminal through resistors R5 and R6, respectively, as opposed to the drain, so that any one of the gates is turned on at any time. A first NMOS transistor NM6 and a second NMOS transistor NM7 having the voltage level of the terminal " low "; A drain is connected to the first input terminal and a second input terminal of the third transistor and the fourth transistor, respectively, and a source is commonly connected to the first output terminal. ) Is connected to the first input terminal and the second input terminal through the resistors R5 and R6, respectively, in contrast to the drain, so that any one of the conduction is conducted at any time, thereby reducing the voltage level of the first output terminal. And a third NMOS transistor (NM8) and a fourth NMOS transistor (NM9). The drain and drain terminals of the first transistor and the second transistor are connected to the first input terminal and the second input terminal, respectively, and the source is commonly connected to the second output terminal. The gate is connected to the first input terminal and the second input terminal through resistors R7 and R8, respectively, as opposed to the drain, so that any one of the gates is turned on at any point in time. A first PMOS transistor PM6 and a second PMOS transistor PM7 whose voltage level of the terminal is " low "; A drain and a drain are respectively connected to the first and second input terminals of the third and fourth transistors, and a source is commonly connected to the first output terminal, respectively, and a gate is connected to the first and second input terminals. In contrast to the drain, is connected by the second input terminal and the first input terminal through the resistors R7 and R8, respectively, so that any one of the conduction is conducted at any time, thereby reducing the voltage level of the first output terminal. And a fourth PMOS transistor (PM8) and a fourth PMOS transistor (PM9).