KR950000150B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

The invention relates to a method for preventing emitter-base junction region of Bipolar transistor from damaging. The method comprises: the first step of forming a side-wall spacer on the gate side-wall of the second MOS transistor, and source/drain in which a high concentration impurity of first conductive type is doped; and the second step of forming a side-wall spacer on the gate side-wall of the first MOS transistor to etch the oxide film for spacer formation and ion-implant, and source/drain in which the high concentration impurity of second conductive type is doped, and an extrinsic base region of the Bipolar transistor.

Description

Manufacturing Method of Semiconductor Device

1A to 1I are cross-sectional views of a process sequence showing a method for manufacturing a BiCMOS semiconductor device according to the prior art.

2A to 2J are cross-sectional views of a process sequence showing a method for manufacturing a BiCMOS semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for preventing damage to an emitter-base junction region of a bipolar transistor when forming a spacer for an LDD structure in a BiCMOS.

Although CMOS transistors have a complicated manufacturing process, a large occupied area of the device, and the latch-up phenomenon, which is a major problem, cannot be avoided, power consumption, operating voltage and operation are small. The temperature range is wide and the noise margin is large, so it is widely used. The improvement of the operation speed of CMOS devices is further spurred by the miniaturization of devices, and CMOS has advanced into the high-speed LSI field. Accordingly, researches on BiCMOS, which properly combines bipolar transistors and CMOS transistors with high-speed operation characteristics, are being actively conducted.

The goal of these processes is to combine bipolar devices into a load with the large capacity required to drive the dense logic circuits provided by conventional CMOS technology.

Since the few bipolar transistors do not drive the power consumption of the chip, even if the bipolar transistor is biased with a relatively large current value of about 1 to 100 mA, an optimized bipolar element is needed to take advantage of the high speed.

Meanwhile, among the various constraints imposed on the device, researches to improve the breakdown voltage between the drain and the source by optimizing the device structure and the device parameters have been actively conducted. ) was a proposal such as the structure, the two structures are all N of the drain and source ^region, the diffusion layer or P ^- diffusion layers have a large effect on inhibition occurs in chamber pressed flower and carrier (Hot carrier). However, the manufacturing process of DDD structure is simpler than that of LDD structure, but short channel effect is more likely to occur than LDD structure. Therefore, DDD structure is used for 2μm line width technology and LDD structure for 1μm line width technology. have. Considering the process of forming the LDD structure in accordance with the object of the present invention, the LDD structure proposed by Ogura has the same basic concept as the offset gate MOS transistor used in the high voltage breakdown device or high breakdown voltage IC of the company. However, in the conventional offset gate MOS transistor, since one offset mask is added to form an offset region, a problem arises in that the length of the offset region is changed to a mask matching error. In the LDD structure, the length of the offset region is strictly controlled by a spacer formed on the side of the gate electrode without adding a mask. When investigated the spacer forming process of gate electrode formation, and N or P in the low-concentration diffusion ^{layer-subjected} to ion implantation for layer formation and 2000Å to the insulating film of 5000Å or so, typically deposited on the semiconductor substrate and the gate electrode is formed, a CVD oxide film do. When the insulating layer is etched by anisotropic etching by reactive ion etching (RIE), the insulating layer may remain on only sidewalls of the gate electrode to form a spacer. After the formation of the spacer, the N ⁺ layer is formed by ion implantation as in the MOS transistor having the conventional structure. As described above, the formation of the spacer is important in the LDD structure.

However, in the BiCMOS when forming the spacer emitter-base junction of the emitter of the blossomed damage to the silicon substrate surface is etched in progress in the base active region to be formed bipolar transistor, the leakage current between the base is causing a linear current amplification factor H _FE Properties become poor. In order to solve this problem, when etching the insulating film to form a spacer, first, etching is performed by dry etching so as not to damage the base active region, and then etching is performed by wafer wet etching, thereby preventing damage by dry etching to the base active region. In some cases, a two-step etching process may be performed to prevent the occurrence of deterioration of the MOS transistor due to damage of the spacer by isotropic etching during wet etching.

An example of manufacturing a BicMOS semiconductor device by the prior art will be described with reference to FIGS. 1A to 1I.

A; (3 Deep n ⁺ sinker) and field oxide film 4, the Figure 1a the n- well (1), p- well 2, the deep n ⁺ sinker on a semiconductor substrate through a conventional process, as shown in Form.

Subsequently, as shown in FIG. 1B, for example, an oxide film is used to form the gate insulating film 5, and then polysilicon is deposited on the gate insulating film 5 as a material for forming the gate electrode. The photolithography process is performed to form the gate electrode 6. Then the ion implantation of the lightly doped n- nMOSD to the source / drain regions 27 and the pMOS P to form an LDD structure, ^each of the source / drain region 7, after forming side wall spacers on the output front ( 8) For example, an oxide film 8 is formed.

Next, as shown in FIG. 1C, the spacer oxide layer 8 is completely dry-etched to form the gate electrode 6 of the nMOS and pMOS layers at the same time.

Subsequently, as shown in FIG. 1, after forming the photoresist pattern 9 for forming N ⁺ source / drain of the nMOS, N ⁺ ion implantation is performed to form the N ⁺ source / drain region 27.

Next, as shown in FIG. 1E, after forming the photoresist pattern 10 for forming the P ⁺ source / drain region and the extrinsic base region of the pMOS, p ⁺ ion implantation is performed. The P ⁺ source / drain 7 'region and the extrinsic base region 11 are simultaneously formed.

Subsequently, as shown in FIG. 1, after forming the photoresist pattern 12 for defining the base region 13, ion implantation is performed to form the base region 13.

Next, as shown in FIG. 1G, an interlayer insulating film 14 is formed on the entire surface of the resultant product, and then a photoresist pattern 15 for emitter formation is formed on the interlayer insulating film 14.

Subsequently, after removing the interlayer insulating film 14 on the emitter region using the emitter forming photoresist pattern as shown in FIG. 1n, the polysilicon 16 for forming the emitter is deposited on the entire surface of the resultant. A photoresist pattern 17 for forming an emitter polysilicon pattern is formed.

Next, as shown in FIG. 1I, the polysilicon emitter 18, the interlayer insulating film 19, and the metal terminal 20 are formed by conventional methods.

In the BiCMOS semiconductor device according to the prior art described above, the emitter-base junction is exposed during the entire dry etching of the spacer oxide film for forming the sidewall spacers (see FIG. 1c), and is thus damaged. This damage ultimately acts as a factor in degrading the H _FE of the device.

Accordingly, an object of the present invention is to protect the emitter-base junction region during photolithography for forming sidewall spacers with a photoresist pattern in BiCMOS semiconductor devices, thereby preventing damage and having excellent H _FE characteristics.

In order to achieve the above object, the present invention provides a first MOS transistor comprising a source and a drain and a gate of an LDD structure formed by diffusion of impurities of a second conductivity type into a well of a first conductivity type, and a first into a well of a second conductivity type. A second MOS transistor comprising a source and a drain and a gate of an LDD structure formed by diffusion of a conductive impurity, and a base and a collector formed by diffusing a second conductive impurity in a well of a first conductive type, in the base region A method of manufacturing a semiconductor device comprising a bipolar transistor comprising an emitter formed by diffusion of impurities of a first conductivity type, wherein the wells of the first conductivity type, the wells of the second conductivity type, and the impurities of the first conductivity type Highly doped deep sinkers, field oxide films, gates of the first and second MOS transistors, and impurities of the second conductivity type are low. On the semiconductor substrate on which the source and drain of the first MOS transistor formed by being diffused back and the source and drain of the second MOS transistor formed by diffusion of impurities of the first conductivity type at low concentration and the base are formed at predetermined positions, respectively. After forming the spacer forming oxide film and the first photoresist pattern in sequence, the entire surface of the spacer forming oxide film is dry-etched and ion implanted using the first photoresist pattern as a mask to form sidewall spacers on the gate sidewall of the second MOS transistor. In addition, the first step of forming a source and a drain doped with a high concentration of impurities of a first conductive type, after removing the first photoresist pattern, a second photoresist pattern is formed on the entire surface of the resultant, and the second photoresist is formed. The spacer forming oxide film exposed using a pattern as a mask Forming a sidewall spacer on the sidewall of the gate of the first MOS transistor by dry etching and ion implantation of the first MOS transistor, and forming a source and a drain doped with a high concentration of impurities of a second conductivity type and an extrinsic base region of the bipolar transistor. It provides a semiconductor device manufacturing method comprising a second step.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

n-well (1), p-well (2), deep n ⁺ sinker (3) field oxide (4), gate insulating and gate electrodes (5,6), n- source / drain regions (27) and p- Since the steps up to forming the source / drain regions 7 are the same as those of the conventional method described above, the description thereof is omitted.

As shown in FIG. 2A, first, the photoresist pattern 21 for defining the base region is formed, and then p ⁻ ion implantation is performed to form the base region 13.

Subsequently, as shown in FIG. 2B, the photoresist pattern is removed and the oxide film 8 is deposited to a thickness of 2000 kV to 3000 kV, for example, as a sidewall spacer forming film on the entire surface of the resultant.

Next, as shown in FIG. 2C, a photoresist pattern 22 for forming n ⁺ source / drain regions is formed on the oxide film 8.

Next, as shown in FIG. 2D, front side etching is provided to form sidewall spacers 8 on the gate sidewalls of the nMOS. At this time, the surface of the base region 13 is not damaged by the entire dry etching process for forming the spacers by the oxide film 8 remaining under the photoresist pattern 22. Subsequently, n ⁺ ion implantation using n-type impurities such as phosphorus (P) is performed to form n ⁺ source / drain regions 27.

Next, as shown in FIG. 2E, the photoresist pattern for forming the n ⁺ source / drain region is removed, and then the photoresist is applied to the entire surface of the resultant, and the extrinsic base region and p ⁺ source / are subjected to the photolithography process. The photoresist pattern 23 for forming the drain region is formed.

Subsequently, as shown in FIG. 2F, dry etching is performed to remove the oxide film 8 on the extrinsic base region and to form a spacer 8 on the sidewalls of the pMOS gate, and then p-type impurities such as boron ( p ⁺ ion implantation using b) is performed to form p ⁺ extrinsic base region 11 and p ⁺ source / drain region 7 '. At this time, the base region 13 except for the p ⁺ extrinsic base region 11 is protected from damage of the dog etch by the photoresist pattern 23.

Next, as shown in FIG. 2G, the photoresist pattern is removed, an interlayer insulating film 14 is formed on the entire surface of the resultant, and the photoresist pattern is applied thereon. The photoresist pattern for emitter formation is then formed by a photolithography process. To form (24).

Since the process of forming the polysilicon emitter (16,18) interlayer insulating film 19 and the metal terminal 20 shown in Figs. 2h, 2i, and 2j is the same as the conventional prior art described above, Description is omitted. However, the spacer film 8 for spacer formation, which has not been removed, remains partially on the n-well region 1 in which the base region 13 is formed.

Or more in the production in the BiCMOS semiconductor device according to the present invention, as discussed above, the emitter-as that damage is minimized by being base junction region is covered by the photoresist pattern during dry etching for forming a sidewall spacer for LDD structure H _FE BiCMOS semiconductor devices with bipolar transistors with excellent linearity can be realized.

Claims (5)

A first MOS transistor comprising a source and a drain and a gate of an LDD structure formed by diffusion of impurities of a second conductivity type into a well of a first conductivity type, and an LDD formed by diffusion of impurities of a first conductivity type into a well of a second conductivity type. A second MOS transistor composed of a source and a drain and a gate of the structure, and a base and a collector formed by diffusing a second conductive type impurity into a well of a first conductive type, and formed by diffusing a first conductive type impurity into the base region. A method of manufacturing a semiconductor device comprising a bipolar transistor composed of an emitter, the method comprising: a well-type well of a first conductivity type, a well of a second conductivity type, a deep sinker doped with a high concentration of impurities of a first conductivity type, a field oxide film, Each of the gates of the first MOS transistor and the second MOS transistor, and the first MOS transistor formed by diffusion of impurities of a second conductivity type at low concentration. An oxide film and a first photoresist for forming a spacer on a semiconductor substrate having a source and a drain of the second MOS formed by diffusion of a low concentration of impurities of a first conductivity type and a source and a drain of the first conductive type; After the patterns were formed in turn, the second photoresist pattern was used as a mask to dry-etch and ion-implant the spacer forming oxide film to form sidewall spacers on the gate side walls of the second MOS transistors. A first process of forming a source and a drain doped with a high concentration of impurities, and after removing the first photoresist pattern to form a second photoresist pattern on the entire surface of the resultant, the spacer is exposed using the second photoresist pattern as a mask The first MOS transistor is dry-etched and ion implanted to form an oxide film. And forming a sidewall spacer on the gate sidewall of the gate, and forming a source and a drain doped with a high concentration of impurities of the second conductivity type and an extrinsic base region of the bipolar transistor. Method of preparation. The method of claim 1, wherein the first photoresist pattern is a pattern formed on the first MOS transistor region and the bipolar transistor region by a photolithography process. The semiconductor of claim 1, wherein the second photoresist pattern is formed by a photolithography process such that only a portion of the spacer forming oxide film remaining on the first MOS transistor region and the bipolar transistor region is exposed. Method of manufacturing the device. The method of claim 1, wherein after the second process, the second photoresist pattern is removed, and an interlayer insulating film is formed on the entire surface of the resultant, and a photoresist pattern for forming an emitter of a bipolar transistor is formed on the interlayer insulating film by a photolithography process. Removing the interlayer insulating film using the photoresist pattern, and then depositing polysilicon for emitter formation on the entire surface of the resultant, and then forming a photoresist pattern for forming the emitter polysilicon pattern, followed by And forming a polysilicon emitter, an interlayer dielectric film, and a metal terminal by the step of. The method of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.