KR940027330A - Control device and method of variable length code decoder - Google Patents

Control device and method of variable length code decoder Download PDF

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Publication number
KR940027330A
KR940027330A KR1019930008912A KR930008912A KR940027330A KR 940027330 A KR940027330 A KR 940027330A KR 1019930008912 A KR1019930008912 A KR 1019930008912A KR 930008912 A KR930008912 A KR 930008912A KR 940027330 A KR940027330 A KR 940027330A
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South Korea
Prior art keywords
signal
decoder
outputting
barrel shifter
hold
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KR1019930008912A
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Korean (ko)
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KR950013875B1 (en
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최종식
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이헌조
주식회사 금성사
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Priority to KR1019930008912A priority Critical patent/KR950013875B1/en
Publication of KR940027330A publication Critical patent/KR940027330A/en
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Publication of KR950013875B1 publication Critical patent/KR950013875B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

본 발명은 가변장 부호 복호기의 제어장치에 관한 것으로, 종래에는 1프레임시간에 1프레임분의 코딩데이타를 처리하기 위해 디코더클럭 자체를 죽이는 방법을 사용하기 때문에 시스템의 불안정이 초래되며 디코딩 작업이 쉬고 있는 동안 디코더 클럭이 없으므로 다른 작업을 수행하지 못하는 문제점이 있다.The present invention relates to a control device of a variable length code decoder. In the related art, since a method of killing the decoder clock itself is used to process one frame of coding data in one frame time, system instability is caused and decoding is easy. There is no decoder clock while there is a problem that can not do anything else.

따라서 종래의 문제점을 해결하기 위하여 본 발명은 디코딩동작이 쉬고 있는 동안에도 클럭이 살아 있으므로 이를 이용해 그동안에 필요한 다른 여분의 일을 수행할 수 있도록 한 효과가 있다.Therefore, in order to solve the conventional problem, the present invention has an effect that the clock is alive even while the decoding operation is stopped, so that it is possible to perform other extra work required in the meantime.

Description

가변장 부호 복호기의 제어장치 및 방법Control device and method of variable length code decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 3 도는 본 발명 가변장 부호 복호기의 제어장치 구성도, 제 4 도는 본 발명 가변장 부호 복호기의 제어방법에 대한 흐름도.3 is a configuration diagram of a control device of a variable length code decoder of the present invention, and FIG. 4 is a flowchart of a control method of the variable length code decoder of the present invention.

Claims (2)

디코더시스템 전체에 공급되는 클럭을 공급함과 아울러 프레임동기신호(F-SYNC)를 발생시키는 클럭 발생부(11)와, 이 클럭발생부(11)로부터 프레임 동기신호(F-SYNC)가 입력되면 홀드 신호를 하이상태로 픽쳐스타트코드(PSC)가 입력되면 홀드신호를 로우상태로 만들어 출력하는 신호제어부(12)와, 상기 신호제어부(12)에 의한 홀드신호(Hold)에 따라 코드워드길이의 전달을 온 또는 오프하도록 하는 앤드게이트(AD1)와, 상기 앤드게이트(AD1)를 통한 코드워드길이를 누적하여 배럴시프터(15)의 시프트양을 결정하는 시프트제어부(16)와, 상기 시프트제어부(16)의 제어에 의해 데이타를 출력시키는 배럴시프트(15)와, 상기 배럴시프트(15)를 통해 시프트된 데이타를 디코딩하여 처리하는 데이타디코더(13)와, 상기 배럴시프터(15)를 통해 입력되는 코드워드(code word)의 길이를 산출하여 출력하는 랭스터코더(length decoder)(14)로 구성된 가변장 부호 복호기의 제어장치.The clock generator 11 supplies the clock supplied to the entire decoder system and generates the frame synchronization signal F-SYNC, and when the frame synchronization signal F-SYNC is input from the clock generator 11, it is held. Transmitting the codeword length in accordance with the hold signal Hold by the signal controller 12 and the signal controller 12 which makes the hold signal low when the picture start code PSC is inputted with the signal high. An AND gate AD1 for turning ON or OFF, a shift controller 16 for determining a shift amount of the barrel shifter 15 by accumulating the codeword length through the AND gate AD1, and the shift controller 16 A barrel shifter (15) for outputting data under control of the control unit; a data decoder (13) for decoding and processing data shifted through the barrel shifter (15); and a code inputted through the barrel shifter (15). The length of a word Calculating and outputting the master encoder Lang (length decoder) (14) of the long code decoder variable control device consisting of a. 홀드신호가 하이인 상태에서 픽쳐스타트코드(PSC)가 하이상태인가를 체크하는 제 1 단계와, 상기 제 1 단계에서 하이가 아니면 계속해서 체크하고 하이이면 홀드신호를 로우로 만들어 출력하는 제 2 단계와, 상기 제 2 단계가 진행되어가는 상태에서 프레임 동기펄스가 상승에찌인가를 체크하여 상승구간이면 홀드신호를 하이상태로 출력하여 디코딩을 처리하도록 하고 상승구간이 아니면 계속해서 체크하는 제 3 단계와, 상기 제 3 단계가 진행 완료되면 다시 상기 제 1 단계로 되돌아가 반복하도록 함을 특징으로 하는 가변장 부호 복호기의 제어방법.A first step of checking whether the picture start code (PSC) is high when the hold signal is high, and a second step of continuously checking if it is not high in the first step, and making the hold signal low and outputting it if it is high And a third step of checking whether the frame sync pulse is rising edge in the state where the second step is in progress and outputting the hold signal in a high state in the rising period to process decoding, and continuously checking in the non-rising period. And if the third step is completed, returns to the first step and repeats the control. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930008912A 1993-05-22 1993-05-22 Variable coder control apparatus KR950013875B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930008912A KR950013875B1 (en) 1993-05-22 1993-05-22 Variable coder control apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930008912A KR950013875B1 (en) 1993-05-22 1993-05-22 Variable coder control apparatus

Publications (2)

Publication Number Publication Date
KR940027330A true KR940027330A (en) 1994-12-10
KR950013875B1 KR950013875B1 (en) 1995-11-17

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