KR940023175A

KR940023175A - Digital TV Pulse Noise Canceller

Info

Publication number: KR940023175A
Application number: KR1019930004522A
Authority: KR
Inventors: 김종규
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1993-03-23
Filing date: 1993-03-23
Publication date: 1994-10-22

Abstract

본 발명은 디지틀 텔레비젼의 펄스 잡음 제거 장치에 관한 것으로서, 상기 아날로그 영상신호를 샘플링하고, 각각의 샘플들을 다수의 비트로 구성된 디지틀 데이타로 변환하며, 상기 디지탈 데이타를 병렬로 동시에 출력하는 아날로그/디지탈 변환수단과; 상기 병렬 디지틀 데이타를 이용하여 펄스 잡음이 위치한 샘플 데이타를 검출함으로써 펄스 잡음을 검출하는 수단과; 상기 아날로그/디지틀 변환 수단으로부터 샘플데이타 단위의 디지틀 데이타를 입력받고, 제1클록 신호에 따라 1샘플 데이타씩 지연시켜 출력하는 제1지연수단과; 상기 제1지연수단으로부터 샘플 데이타 단위의 디지틀 데이타를 입력받고, 제2클록 신호에 따라 1샘플 데이타씩 지연시켜 출력하는 제2지연 수단과; 상기 제1지연 수단 및 제2지연 수단의 출력데이타를 입력받고, 펄스 잡음이 검출안될 경우 상기 제1지연 수단의 출력 데이타를, 펄스 잡음이 검출될 경우 상기 제2지연 수단의 출력 데이타을 선택하여 출력하는 선택 수단을 포함한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse noise canceling device for a digital television, comprising: analog / digital conversion means for sampling the analog video signal, converting each sample into digital data composed of a plurality of bits, and simultaneously outputting the digital data in parallel and; Means for detecting pulse noise by detecting sample data in which pulse noise is located using the parallel digital data; First delay means for receiving digital data in the unit of sample data from the analog / digital converting means and delaying and outputting one sample data according to a first clock signal; Second delay means for receiving digital data in a unit of sample data from the first delay means and delaying one sample data in accordance with a second clock signal to output the delayed data; The output data of the first delay means and the second delay means is input, and if the pulse noise is not detected, the output data of the first delay means is selected and the output data of the second delay means is selected if the pulse noise is detected. And selection means.

Description

Digital TV Pulse Noise Canceller

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 펄스 잡음 제거 회로도, 제4도는 제2도의 회로도에 의한 펄스 잡음 제거 예를 도시하는 도면.FIG. 3 is a pulse noise canceling circuit diagram according to the present invention, and FIG. 4 is a diagram showing an example of pulse noise canceling by the circuit diagram of FIG.

Claims

An analog / digital converting means for removing pulse noise included in an analog video signal, sampling the analog video signal, converting each sample into digital data consisting of a plurality of bits, and simultaneously outputting the digital data in parallel. and; Means for detecting pulse noise by detecting sample data in which pulse noise is located using the parallel digital data; First delay means for receiving digital data in the unit of sample data from the analog / digital conversion means, and delaying and outputting one sample data according to a first clock signal; Second delay means for receiving digital data in a unit of sample data from the first delay means, and delaying and outputting one sample data according to a second clock signal; The output data of the first delay means and the second delay means is input, and if the pulse noise is not detected, the output data of the first delay means is selected, and if the pulse noise is detected, the output data of the second delay means is selected. Perth noise canceller comprising a selection means for outputting.

2. The apparatus of claim 1, further comprising means for disabling said second clock signal upon detection of said pulse noise, said selecting means for continuing to select output data of said second delay means when pulse noise occurs continuously. Pulse noise canceller.

※ Note: The disclosure is based on the initial application.