KR940023025A - Data Output Buffer of Semiconductor Integrated Circuits Adaptable to Multiple Operating Voltages - Google Patents

Data Output Buffer of Semiconductor Integrated Circuits Adaptable to Multiple Operating Voltages Download PDF

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Publication number
KR940023025A
KR940023025A KR1019930005328A KR930005328A KR940023025A KR 940023025 A KR940023025 A KR 940023025A KR 1019930005328 A KR1019930005328 A KR 1019930005328A KR 930005328 A KR930005328 A KR 930005328A KR 940023025 A KR940023025 A KR 940023025A
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South Korea
Prior art keywords
voltage
data output
output buffer
pull
boost
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KR1019930005328A
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Korean (ko)
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KR960000603B1 (en
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김명재
이규찬
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)

Abstract

본 발명은 반도체집적회로에서 특히 다수개의 동작전압에 적응가능한 데이타출력버퍼를 개시하고 있다. 본 발명에 대한 데이타출력버퍼는 전원공급전압의 전압레벨이 제1상태에 있을시에는 출력용 풀엎단을 승압시키는 부우스트노드의 프리차아지상태를 유지시키고 전원공급전압의 전압레벨이 제2상태에 있을시에는 상기 부우스트노드를 상기 프리차아지상태 이상으로 미리 부우스트시키도록 하는 부우스트제어회로를 구비한다. 따라서 예컨대 5V와 3.3V 겸용으로 제조되는 칩에서 풀엎단 제어전압을 부우스트하기 위해 마스크를 2단으로 사용하여야 하는 불편함이 제거된다. 또한 단일 마스크를 사용함에 따라 제조공정 및 비용의 절감이 향상된다. 또한 전원공급전압 VCC의 전압레벨이 현저히 낮아지는 경우에도 출력용 풀엎단으로 공급되는 높은 부우스트전압을 얻을 수 있으며, 동시에 고속으로 전압상승이 이루어지는 효과가 있다.The present invention discloses a data output buffer which is particularly adaptable to a plurality of operating voltages in a semiconductor integrated circuit. The data output buffer according to the present invention maintains the precharge state of the boost node which boosts the output pull-up when the voltage level of the power supply voltage is in the first state and the voltage level of the power supply voltage is in the second state. And a boost control circuit for boosting the boost node in advance above the precharge state. This eliminates the inconvenience of having to use a mask in two stages to boost the pull-down control voltage, for example, on chips manufactured for both 5V and 3.3V. The use of a single mask also improves manufacturing processes and costs. In addition, even when the voltage level of the power supply voltage VCC is significantly lowered, a high boost voltage supplied to the output stack can be obtained, and at the same time, the voltage rises at a high speed.

Description

다수개의 동작전압에 적응가능한 반도체집적회로의 데이타출력버퍼Data Output Buffer of Semiconductor Integrated Circuits Adaptable to Multiple Operating Voltages

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 다수개의 동작전압에 적응가능한 반도체집적회로의 데이타출력버퍼의 일 실시예를 보여주는 회로도, 제3도는 제2도의 레벨변환회로의 상세회로도, 제4도는 본 발명에 의한 다수개의 동작전압에 적응가능한 반도체집적회로의 데이타출력버퍼의 다른 실시예를 보여주는 회로도.2 is a circuit diagram showing an embodiment of a data output buffer of a semiconductor integrated circuit which is adaptable to a plurality of operating voltages according to the present invention, FIG. 3 is a detailed circuit diagram of the level conversion circuit of FIG. 2, and FIG. Circuit diagram showing another embodiment of a data output buffer of a semiconductor integrated circuit adaptable to two operating voltages.

Claims (5)

서로 상보적으로 동작하는 출력용 풀앞단 및 풀다운단을 가지며, 상기 풀엎단의 제어신호를 승입시키기 위한 부우스트노드를 가지는 반도체집적회로의 데이타출력버퍼에 있어서, 상기 부우스트노드에 연결되고, 전원공급전압의 전압레벨이 제1상태에 있을시에는 상기 부우스트노드의 프리차아지상태를 유지시키고 상기 전원공급전압의 전압레벨이 제2상태에 있을시에는 상기 부우스트노드를 상기 프리차아지상태 이상으로 미리 부우스트시키도록 하는 부우스트제어회로를 구비함을 특징으로 하는 데이타출력버퍼.A data output buffer of a semiconductor integrated circuit having an output pull front end and a pull down end that operate complementarily to each other, and having a boost node for accepting a control signal of the pull end, wherein the data output buffer is connected to the boost node and supplied with power. When the voltage level of the voltage is in the first state, the precharge state of the boost node is maintained. When the voltage level of the power supply voltage is in the second state, the boost node is equal to or greater than the precharge state. And a boost control circuit for boosting the signal in advance. 제1항에 있어서, 상기 제1상태의 전압레벨이 상기 제2상태의 전압보다 더 높음을 특징으로 하는 데이타출력버퍼.The data output buffer as claimed in claim 1, wherein the voltage level of the first state is higher than that of the second state. 제1항에 있어서, 상기 부우스트제어회로가 상기 전원공급전압의 전압레벨을 검출하는 전압검출회로를 구비함을 특징으로 하는 데이타출력버퍼.2. The data output buffer as set forth in claim 1, wherein said boost control circuit includes a voltage detection circuit for detecting a voltage level of said power supply voltage. 서로 상보적으로 동작하는 출력용 풀엎단 및 풀다운단을 가지며, 상기 풀엎단의 제어신호를 승압시키기 위한 부우스트노드를 가지는 반도체집적회로의 데이타출력버퍼에 있어서, 칩 외부에서 공급되는 전원공급전압의 전압레벨에 응답하여 미리 예정된 신호를 출력하는 전압검출회로와, 상기 전압검출회로의 출력신호와 데이타출력인에이블신호를 각각 입력하는 논리부와, 상기 논리부의 출력단에 전극의 일단이 접속되는 펌핑캐패시터와, 상기 데이타출력버퍼의 구동신호를 입력하는 레벨변환회로와, 상기 펌핑캐패시터와 상기 부우스트노드사이를 스위칭접속하고 상기 레벨변환회로의 출력신호에 응답하여 스위칭동작이 이루어지는 전송수단을 구비함을 특징으로 하는 데이타출력버퍼.A data output buffer of a semiconductor integrated circuit having an output pull-down and pull-down stages which operate complementarily to each other, and a boost node for boosting the control signal of the pull-up, wherein the voltage of the power supply voltage supplied from the outside of the chip A voltage detection circuit for outputting a predetermined signal in response to the level, a logic unit for inputting an output signal and a data output enable signal of the voltage detection circuit, a pumping capacitor having one end of an electrode connected to an output terminal of the logic unit, and And a level converting circuit for inputting a drive signal of the data output buffer, and switching means for switching between the pumping capacitor and the boost node and for switching in response to an output signal of the level converting circuit. Data output buffer. 서로 상보적으로 동작하는 출력용 풀엎단 및 풀다운단을 가지며, 상기 풀엎단의 제어신호를 승압시키기 위한 부우스트노드를 가지는 반도체집적회로의 데이타출력버퍼에 있어서, 칩 외부에서 공급되는 전원공급전압의 전압레벨에 응답하여 미리 예정된 신호를 출력하는 전압검출회로와, 상기 전압검출회로의 출력신호와 메모리셀로부터 독출된 데이타와 데이타출력버퍼의 구동신호를 각각 조합입력하는 논리부와, 상기 논리부의 출력단과 상기 부우스트노드사이에 전극의 양단이 접속되는 펌핑캐패시터를 구비하는 데이타출력버퍼.A data output buffer of a semiconductor integrated circuit having an output pull-down and pull-down stages which operate complementarily to each other, and a boost node for boosting the control signal of the pull-up, wherein the voltage of the power supply voltage supplied from the outside of the chip A voltage detection circuit for outputting a predetermined signal in response to a level, a logic section for combining and inputting an output signal of the voltage detection circuit, data read from a memory cell, and a drive signal of a data output buffer, and an output terminal of the logic section; And a pumping capacitor connected at both ends of the electrode between the boost nodes. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930005328A 1993-03-31 1993-03-31 Output buffer of semiconductor integrated circuit KR960000603B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980010693A (en) * 1996-07-01 1998-04-30
KR100465599B1 (en) * 2001-12-07 2005-01-13 주식회사 하이닉스반도체 Data output buffer
KR100487481B1 (en) * 1997-05-24 2005-07-29 삼성전자주식회사 Semiconductor memory device having data output driving circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980010693A (en) * 1996-07-01 1998-04-30
KR100487481B1 (en) * 1997-05-24 2005-07-29 삼성전자주식회사 Semiconductor memory device having data output driving circuit
KR100465599B1 (en) * 2001-12-07 2005-01-13 주식회사 하이닉스반도체 Data output buffer

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