KR940020550A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940020550A
KR940020550A KR1019930003018A KR930003018A KR940020550A KR 940020550 A KR940020550 A KR 940020550A KR 1019930003018 A KR1019930003018 A KR 1019930003018A KR 930003018 A KR930003018 A KR 930003018A KR 940020550 A KR940020550 A KR 940020550A
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KR
South Korea
Prior art keywords
metal
metal oxide
manufacturing
oxide film
forming
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Application number
KR1019930003018A
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Korean (ko)
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KR950010873B1 (en
Inventor
김진우
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김광호
삼성전자 주식회사
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Priority to KR1019930003018A priority Critical patent/KR950010873B1/en
Publication of KR940020550A publication Critical patent/KR940020550A/en
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Publication of KR950010873B1 publication Critical patent/KR950010873B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

Abstract

본 발명은 프로그램가능한 접속소자(programmable interconnect devices;PID)용 안티퓨즈 제조방법에 관한 것이다.The present invention relates to a method for manufacturing antifuse for programmable interconnect devices (PID).

본 발명에 의한 PID용 안티퓨즈 제조방법은 PID용 안티퓨즈콘택과 금속콘택을 동시에 형성하는 공정과 안티퓨즈 막질로서 금속산화막을 형성하는 공정으로 이루어지는 것을 특징으로 한다.PID anti-fuse manufacturing method according to the invention is characterized in that it comprises a step of forming a PID anti-fuse contact and a metal contact at the same time and a step of forming a metal oxide film as the anti-fuse film quality.

본 발명에 의하면, 최소한의 포토리소그래픽공정에 의해 ID용 안티퓨즈를 형성할 수 있으며, 금속산화막을 안티퓨즈막으로 사용함으로써 막질의 두께를 조절할 수 있고 누설전류를 감소시킬 수 있어 안정된 소자동작을 얻을 수 있다.According to the present invention, the anti-fuse for ID can be formed by a minimum photolithographic process, and the thickness of the film can be controlled and the leakage current can be reduced by using the metal oxide film as the anti-fuse film. You can get it.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제7도 내지 제11도는 본 발명에 의한 PID용 안티퓨즈 제조방법을 도시한 공정순서도.7 to 11 are process flowcharts illustrating a method for manufacturing antifuse for PID according to the present invention.

Claims (6)

반도체기판상에 하부도전층을 형성하는 공정; 상기 하부도전층상에 절연층을 형성하는 공정; 상기 하부도전층의 소정부분을 노출시키기 위해 상기 절연층에 안티퓨즈 콘택개구부 및 금속 콘택개구부를 동시에 형성하는 공정; 상기 결과물 전면에 금속산화막을 형성하는 공정; 상기 안티퓨즈 콘택영역에만 상기 금속산화막을 남기는 공정; 상기 결과물 전면에 금속을 증착한 후 이를 소정패턴으로 패터닝하여 상기 안티퓨즈 콘택영역의 상기 남아있는 금속산화막의 상부 및 상기 금속 콘택영역상에 상부도전층을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.Forming a lower conductive layer on the semiconductor substrate; Forming an insulating layer on the lower conductive layer; Simultaneously forming an antifuse contact opening and a metal contact opening in the insulating layer to expose a predetermined portion of the lower conductive layer; Forming a metal oxide film on the entire surface of the resultant product; Leaving the metal oxide film only in the anti-fuse contact region; Depositing a metal on the entire surface of the resultant and then patterning the metal in a predetermined pattern to form an upper conductive layer on the remaining metal oxide layer of the anti-fuse contact region and on the metal contact region. Manufacturing method. 제1항에 있어서, 상기 금속산화막은 금속을 증착한 후 산화공정에 의해 상기 금속을 산화시켜 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the metal oxide film is formed by depositing a metal and then oxidizing the metal by an oxidation process. 제2항에 있어서, 상기 금속은 Ti, Al, Ba, Ge, Sn, Be, Nb 및 Ta 중에서 선택한 어느 하나임을 특징으로 하는 반도체장치의 제조방법.The method of claim 2, wherein the metal is any one selected from Ti, Al, Ba, Ge, Sn, Be, Nb, and Ta. 제2항에 있어서, 상기 산화공정은 400℃~800℃의 온도 범위에서 행하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 2, wherein the oxidation step is performed at a temperature in the range of 400 ° C to 800 ° C. 제1항에 있어서, 상기 금속산화막은 금속가스를 산소플라즈마에 통과시켜 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the metal oxide film is formed by passing a metal gas through an oxygen plasma. 제1항에 있어서, 상기 상부도전층은 반도에기판에 형성된 불순물확산영역, 불순물이 도우프된 폴리실리콘층, 폴리사이드층 또는 반도체기판의 도전영역임을 특징으로 하는 프로그램가능한 접속소자의 제조방법.The method of claim 1, wherein the upper conductive layer is an impurity diffusion region formed on a substrate on a peninsula, a polysilicon layer doped with impurities, a polyside layer, or a conductive region of a semiconductor substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930003018A 1993-02-27 1993-02-27 Semiconductor device KR950010873B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930003018A KR950010873B1 (en) 1993-02-27 1993-02-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930003018A KR950010873B1 (en) 1993-02-27 1993-02-27 Semiconductor device

Publications (2)

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KR940020550A true KR940020550A (en) 1994-09-16
KR950010873B1 KR950010873B1 (en) 1995-09-25

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10950707B2 (en) 2002-08-12 2021-03-16 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11018237B2 (en) 2002-08-12 2021-05-25 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel
US11056569B2 (en) 2002-08-12 2021-07-06 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11355613B2 (en) 2002-08-12 2022-06-07 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11610974B2 (en) 2011-11-23 2023-03-21 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11804533B2 (en) 2011-11-23 2023-10-31 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US11462643B2 (en) 2016-11-18 2022-10-04 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

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KR950010873B1 (en) 1995-09-25

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