KR940020428A - Memory redundancy circuit - Google Patents

Memory redundancy circuit Download PDF

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Publication number
KR940020428A
KR940020428A KR1019930002333A KR930002333A KR940020428A KR 940020428 A KR940020428 A KR 940020428A KR 1019930002333 A KR1019930002333 A KR 1019930002333A KR 930002333 A KR930002333 A KR 930002333A KR 940020428 A KR940020428 A KR 940020428A
Authority
KR
South Korea
Prior art keywords
spare
defect
repaired
redundancy
memory
Prior art date
Application number
KR1019930002333A
Other languages
Korean (ko)
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KR100266624B1 (en
Inventor
전용주
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019930002333A priority Critical patent/KR100266624B1/en
Publication of KR940020428A publication Critical patent/KR940020428A/en
Application granted granted Critical
Publication of KR100266624B1 publication Critical patent/KR100266624B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

본 발명은 메모리 리던던시 기술에 관한 것으로, 종래의 리던던시 시스템에 있어서는 불필요한 스페어라인이 소요되고, 또한 스페어 셀 자체의 존재할 확률이 높은 단점이 있으며, 디펙트 워드라인 한쪽 블록에 집중되어 있을 경우, 비록 디펙트 어드레스가 소수일 경우라도 서브블로내에 스페어 워드라인의 수보다 많으면 구제할 수 없게되는 결함이 있었는 바, 본 발명은 이를 해결하기 위하여 메인 디코더의 수를 추가하고 리던던시 디코더에 블록 코딩기능을 추가하여 디펙트 워드라인을 구제할 수 있게 함으로써 서브블록내에 존재하는 스페어 워드라인을 다른 서브블록에서 사용할 수 있게 되고, 메모리에서 빈번히 발생되는 디펙트들을 구제할 수 있게한 것이다.The present invention relates to a memory redundancy technique. In the conventional redundancy system, an unnecessary spare line is required, and there is a high possibility of the existence of the spare cell itself. Even if the number of defect addresses is small, there is a defect that cannot be repaired if the number of spare word lines is larger than the number of spare words. In order to solve the problem, the present invention adds the number of main decoders and the block coding function to the redundancy decoder. By allowing the defect word line to be repaired, the spare word line existing in the sub block can be used in another sub block, and defects frequently occurring in the memory can be repaired.

Description

메모리 리던던시 회로Memory redundancy circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 메로리 리던던시 블록도,3 is a memory redundancy block diagram of the present invention;

제4도는 제3도에서 메인 디코더의 구성도,4 is a configuration diagram of a main decoder in FIG.

제5도는 본 발명의 리던던시 디코더에 대한 상세 회로도.5 is a detailed circuit diagram of a redundancy decoder of the present invention.

Claims (1)

각각 소정 갯수의 스페어 워드라인(SW00-SW01∼SW30-SW31)을 구비한 서브블록(MA0-MA3)과 상기 서브블록(MA0-MA3)내에 있는 디펙트 워드라인을 단속할 수 있는 메인 디코더 퓨즈를 구비한 메인 디코더(MX0-MX3)와, 상기 서브블록(MA0-MA3)을 코딩할 수 있는 퓨즈를 각기 구비한 리던던시 디코더(RD0-RD7)와, 상기 리던던시 디코더 (RD0,RD1-RD6,RD7)와, 메인 디코더(MX0-MX3)를 각기 연결해주는 오아게이트(OR0-OR3)로 구성한 것을 특징으로 하는 메모리 리던던시 회로.Each of the subblocks MA 0 -MA 3 having a predetermined number of spare word lines SW 00 -SW 01 to SW 30 -SW 31 and the defect word lines in the subblocks MA 0 -MA 3, respectively. Redundant decoder RD 0 -RD 7 each having a main decoder (MX 0 -MX 3 ) having a main decoder fuse that can be interrupted, and a fuse capable of coding the subblocks (MA 0- MA 3 ). And a redundancy decoder (OR 0 -OR 3 ) configured to connect the redundancy decoders RD 0 , RD 1 -RD 6 , RD 7 and the main decoders MX 0 -MX 3 , respectively. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930002333A 1993-02-19 1993-02-19 Memory redundancy circuit KR100266624B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930002333A KR100266624B1 (en) 1993-02-19 1993-02-19 Memory redundancy circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930002333A KR100266624B1 (en) 1993-02-19 1993-02-19 Memory redundancy circuit

Publications (2)

Publication Number Publication Date
KR940020428A true KR940020428A (en) 1994-09-16
KR100266624B1 KR100266624B1 (en) 2000-10-02

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930002333A KR100266624B1 (en) 1993-02-19 1993-02-19 Memory redundancy circuit

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KR (1) KR100266624B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100454632B1 (en) * 1997-06-30 2005-04-06 주식회사 하이닉스반도체 Word line repair device for semiconductor devices
KR100505410B1 (en) * 1999-12-23 2005-08-05 주식회사 하이닉스반도체 Row repair circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100454632B1 (en) * 1997-06-30 2005-04-06 주식회사 하이닉스반도체 Word line repair device for semiconductor devices
KR100505410B1 (en) * 1999-12-23 2005-08-05 주식회사 하이닉스반도체 Row repair circuit

Also Published As

Publication number Publication date
KR100266624B1 (en) 2000-10-02

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