KR940017798A - Dynamic Black Level Correction Circuit - Google Patents

Dynamic Black Level Correction Circuit Download PDF

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Publication number
KR940017798A
KR940017798A KR1019920027405A KR920027405A KR940017798A KR 940017798 A KR940017798 A KR 940017798A KR 1019920027405 A KR1019920027405 A KR 1019920027405A KR 920027405 A KR920027405 A KR 920027405A KR 940017798 A KR940017798 A KR 940017798A
Authority
KR
South Korea
Prior art keywords
black level
level
level correction
transistor
correction circuit
Prior art date
Application number
KR1019920027405A
Other languages
Korean (ko)
Other versions
KR0131580B1 (en
Inventor
이종국
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019920027405A priority Critical patent/KR0131580B1/en
Publication of KR940017798A publication Critical patent/KR940017798A/en
Application granted granted Critical
Publication of KR0131580B1 publication Critical patent/KR0131580B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/57—Control of contrast or brightness

Abstract

본 고안은 다이나믹 흑레벨 보정회로에 관한 것으로, 특히 평균 화면 밝기 (Average picture level)의 레벨에 구애받지 않고 다이나믹 흑레벨의 보정을 영상출력단으로 부터 입력신호에 맞추어 보정케하고자 하는것으로, 본 고안은 밝은 화면에서 입체적인 화면을 재생하기 위하여는 평균 화면 밝기(APL)의 레벨에 구애 받지 않고 입력신호에 따라 흑레벨을 보정할수 있게한 다이나믹 흑 레벨 보정회로를 제공하고자하는 것이다.The present invention relates to a dynamic black level correction circuit. In particular, the dynamic black level correction is made to be corrected according to an input signal from an image output terminal regardless of the average picture level. In order to reproduce a three-dimensional screen on a bright screen, it is to provide a dynamic black level correction circuit capable of correcting the black level according to an input signal regardless of the average screen brightness (APL) level.

본 고안은 영상신호 출력단으로 부터의 평균화면 밝기의 레벨을 인지하도록하고, 휘도신호 출력단으로부터 출력되는 신호가 작은가를 판단하도록하여 블랙 레벨 보정 제어부와 화이트 레벨 보정 제어부로 일정전위를 인가하도록 하므로써 평균 화면 밝기(Average picture level)의 레벨에 구애받지 않고 다이나믹 흑레벨의 보정을 영상출력단으로 부터 입력신호에 맞추어 보정케하는 다이나믹 흑레벨 보정회로를 제공하고자 하는 것으로 밝은 화면에서 입체적인 화면을 재생하기 위하여는 평균 화면 밝기(APL)의 레벨에 구애 받지 않고 입력신호에 따라 흑레벨을 보정할수 있게한 것이다.The present invention recognizes the level of the average screen brightness from the video signal output stage, and determines whether the signal output from the brightness signal output stage is small so that a constant potential is applied to the black level correction controller and the white level correction controller. It is intended to provide a dynamic black level correction circuit that corrects the dynamic black level according to the input signal from the video output stage regardless of the level of the brightness (average picture level). The black level can be corrected according to the input signal regardless of the level of the screen brightness (APL).

Description

다이나믹 흑 레벨 보정회로Dynamic Black Level Correction Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 회로도, 제2도는 본 발명의 다이나믹 흑레벨 보정회로도.1 is a conventional circuit diagram, and FIG. 2 is a dynamic black level correction circuit diagram of the present invention.

Claims (1)

흑레벨 보정 제어부(10)와, 화이트 피크 레벨 제어부(20)와, 주전원이 구비된 브라이트 및 콘트라스트 제어부(30)로 이루어진 공지의 흑레벨을 보정하는 것에 있어서, 화이트 피크 레벨제어부(21)의 입력단에 분압저항(R10, R11), 콘덴서(C4), 트랜지스터(Q3)의 콜렉터단에 연결하고, 휘도 신호 입력단(Y-in)에 저항(R1-R4), 콘덴서(C1), 트랜지스터(Q1)로 이루어진 버퍼부(41)를 연결하고, 스탠바이 전원단(ST)에 역전압 방지용 다이오우드(D1)를 구비한 전계 효과 트랜지스터(FET2)의 소스단이 트랜지스터(Q3)의 이미터단에 접속되도록 연결하고, 영상신호 출력단(S-in)에는 바이어스 저항(R5)을 거쳐 트랜지스터(Q3)의 베이스단에 연결하여 구성되는 것을 특징으로 하는 다이나믹 흑 레벨 보정회로.In correcting a known black level composed of a black level correction control unit 10, a white peak level control unit 20, and a bright and contrast control unit 30 provided with a main power source, an input terminal of the white peak level control unit 21 is provided. Connected to the collector terminals of the divided resistors R10 and R11, the capacitor C4 and the transistor Q3, and the resistors R1-R4, the capacitor C1 and the transistor Q1 to the luminance signal input terminal Y-in. A buffer portion 41 formed thereon, and a source terminal of the field effect transistor FET2 having the reverse voltage preventing diode D1 connected to the standby power supply stage ST so as to be connected to an emitter terminal of the transistor Q3. And the video signal output terminal S-in is connected to the base terminal of the transistor Q3 via a bias resistor R5. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027405A 1992-12-31 1992-12-31 Dynamic black level compensation circuits for tv KR0131580B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027405A KR0131580B1 (en) 1992-12-31 1992-12-31 Dynamic black level compensation circuits for tv

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027405A KR0131580B1 (en) 1992-12-31 1992-12-31 Dynamic black level compensation circuits for tv

Publications (2)

Publication Number Publication Date
KR940017798A true KR940017798A (en) 1994-07-27
KR0131580B1 KR0131580B1 (en) 1998-04-16

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ID=19348576

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027405A KR0131580B1 (en) 1992-12-31 1992-12-31 Dynamic black level compensation circuits for tv

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KR (1) KR0131580B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7417669B2 (en) 2003-01-31 2008-08-26 Seiko Epson Corporation Digital clamping circuit and digital clamping method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100747843B1 (en) * 2005-04-29 2007-08-08 엘지전자 주식회사 Method and Apparatus for correcting setup level of image display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7417669B2 (en) 2003-01-31 2008-08-26 Seiko Epson Corporation Digital clamping circuit and digital clamping method

Also Published As

Publication number Publication date
KR0131580B1 (en) 1998-04-16

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