JPS6216068B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a so-called liquid crystal television display device using a liquid crystal display panel as a display element, and more particularly to a video signal processing circuit when an AC drive type liquid crystal such as a guest-host type liquid crystal is used.

Advances in liquid crystal electronics have recently led to the creation of so-called liquid crystal television display devices that use liquid crystals as display elements. This LCD TV utilizes the optical polarization and scattering properties of liquid crystal.
It is generally used in the display parts of clock calculators, etc. Liquid crystal televisions have many advantages, such as requiring a low voltage to be applied to the liquid crystal, consuming little power, and being able to be made thin, making it possible to realize portable television receivers.

There are various types of liquid crystals used in display panels, such as dynamic scattering (DS) type liquid crystals, twisted nematic (TN) type liquid crystals, and guest-host type liquid crystals. DS type liquid crystals have a high contrast and are easy to obtain black-and-white images close to the cathode rays, but they also have drawbacks such as narrow viewing angles, high drive voltage, DC drive (current drive), and significantly short lifespan. The TN guest-host type has advantages such as low voltage operation, low power consumption, and long life because it uses AC drive (electric field drive), making it suitable for use in dry battery-powered portable television receivers. . In order to use the latter AC-driven liquid crystal as a display element, the applied signal (voltage) is supplied as shown in FIG. In the figure, 1 is, for example, a guest-host type liquid crystal. 2
and 3 are electrodes on both sides of the liquid crystal 1 sandwiched therebetween. 4 is an AC signal source. In such a system, when no voltage is applied to the electrodes 2 and 3, the light is absorbed by the dye molecules and no light is transmitted.
When an alternating current signal (for example, a pulse of several hundred Hz) is applied between the electrodes 2 and 3, light passes through the liquid crystal layer, and the amount of transmitted light changes depending on the applied voltage. The idea is to utilize this characteristic to display television image signals.

To display television images, a second
A method using an active matrix type as shown in the figure has been considered. This type of panel is MOS
Active matrix circuits are formed on silicon substrates using IC technology. FIG. 2 is its circuit diagram. In the figure, Y ₁ , Y ₂ , . . . Ym are gate electrodes (address lines), X ₁ , X ₂ , . . . Xn are source electrodes (data lines), 5 is a switching transistor, and 6 is a signal storage capacitor. The signal storage capacitor 6 is connected in parallel with the liquid crystal pixel 1 to the transistor 5, and serves to supplement the capacitance component of the liquid crystal in order to store an image signal for one field period. Pixel selection is performed by switching a switching transistor 5 provided for each pixel. Switching of the transistor 5 is performed on the gate electrodes Y ₁ , Y ₂ ,...Ym row by row, and when the switching transistor in a certain row is in the ON state,
If the image signal voltage of the corresponding pixel is supplied through the source electrodes of X ₁ , X ₂ , ... Maintain image signal voltage. The other pixel electrodes are commonly connected and a predetermined voltage is applied.

To AC drive the liquid crystal display panel as described above, a video signal as shown in FIG. 3 is used.
Source electrodes (data lines) of X ₁ , X ₂ , ...Xn
The power supply voltage of the X driver ( _not shown) for driving the
A voltage of V _DD1 /2 is applied to. In this state, the polarity of the video signal supplied to the X driver is inverted for each field around V _DD1 /2. As a result, the voltage (electric field) applied to the liquid crystal of each pixel is 1
AC drive can be achieved by reversing the positive and negative values for each field.

In such an AC system, if the polarity is not reversed around the common electrode potential _VDD1 /2 but has an offset, a DC voltage is applied to the liquid crystal, which causes current to flow and shorten the life of the liquid crystal. become the cause. Furthermore, the level of the video signal applied to the liquid crystal differs between positive polarity and negative polarity, resulting in a decrease in contrast. Therefore, it is important to design a circuit so that the symmetry of the positive and negative video signals with respect to the common electrode potential is not disrupted due to variations in power supply voltage, temperature changes, and the like. Further, in order to obtain a high contrast ratio, it is desirable to sufficiently swing the video signal within the power supply voltage V _DD1 .

In view of the above-mentioned points, it is an object of the present invention to provide a video signal processing circuit suitable for a liquid crystal television display device using an AC drive type liquid crystal display panel.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram of a video signal processing circuit according to the present invention. The detected video signal is applied to the gamma correction circuit 11 at a predetermined level (and polarity). The gamma correction circuit is a circuit that corrects the gamma (γ=2.2) of the incoming video signal to the gamma of the liquid crystal used. The gamma correction output is applied to a bipolar video signal generation circuit 12 to produce positive and negative video signals with predetermined amplitudes. The peak clamp circuit 13 clamps the peak of the synchronizing signal of each of these video signals to a predetermined DC level. The clamped positive and negative video signals are alternately taken out as positive or negative video signals for each field by the gate circuit 14. The video signal of the gate output is outputted at low impedance via the buffer 15 so as to be able to sufficiently drive the load circuit.

According to the video signal processing method configured as described above, first the gamma is corrected to a predetermined value, and then the correct and correct gamma is corrected.
Amplify the amplitude to a necessary and sufficient level with negative polarity. For example, if the power supply voltage is V _DD1 = 8 V and the common electrode potential is V _DD1 /2 = 4 V, the level from the tip of the synchronizing signal to the white peak is amplified to 4 Vpp. Next, in the peak clamp circuit 13, the leading edge of the synchronizing signal is clamped to a DC level of V _DD1 /2 (=4V) for both positive and negative signals. By extracting positive and negative polarity video signals (4Vpp) for each field from these clamped video signals via the gate circuit 14, an alternating video signal of a desired level as shown in FIG. 3 can be obtained. With such a circuit arrangement, it is possible to obtain a sufficiently swinging video signal from 0v to the power supply voltage V _DD1 without using a particularly high power supply voltage, and it is symmetrical with respect to the common electrode potential V _DD1 /2. You can obtain a video signal with a high quality. For example, in a configuration where a peak clamp circuit and a gate circuit are installed in the front stage to create an alternating video signal and then amplify it to a predetermined level and output it, the power supply voltage must be at least 12V to obtain a video signal of ±4Vpp at the output. This is undesirable because the alternating video signal must be amplified by an amplifier circuit, and it is also troublesome to match the alternating video signal to a level that is inverted around the common electrode potential V _DD1 /2. Furthermore, such a configuration is also vulnerable to fluctuations in power supply voltage.
As mentioned above, it can be seen that the circuit configuration of the present invention described above is advantageous, and the advantages will be further described by showing specific circuit examples. FIG. 5 shows a specific example of the gamma correction circuit 11 and the bipolar video signal generation circuit 12. C ₃ is the coupling capacitor transistor Q ₂₀ , Q ₂₁ resistor,
R ₁₀ , R ₁₁ , R ₁₂ , R ₁₃ , and R ₁₄ constitute a bias circuit. Transistor Q ₂₂ constitutes a peak clamp transistor, and transistor Q ₂₃ and resistor R ₁₅ constitute an emitter follower for buffer. Resistance R ₁₆ ,
R ₁₇ , R ₁₈ and transistors Q ₂₄ and Q ₂₅ constitute a gamma correction circuit, and transistors Q ₂₄ and Q ₂₅ turn on or off in response to a predetermined level of the video signal to switch the gain and adjust the gamma of the video signal. decide. Transistors Q ₂₆ , Q ₂₇ , Q ₂₈ and resistors R ₁₉ , R ₂₀ , R ₂₁ , R ₂₂ constitute a differential amplifier, and a gamma-corrected video signal is applied to the base of transistor Q ₂₆ . An amplified positive video signal is obtained at the collector of the transistor _Q26 , and a similarly negative video signal is obtained at the collector of the transistor _Q27 . These are output via an emitter follower consisting of transistors Q ₂₉ and Q ₃₀ and resistors R ₂₃ and R ₂₄ . The differential amplifier mentioned above has an offset, and transistors _Q26 and _Q27
The base bias of is shifted. For example, bias is set so that the current ratio is IQ ₂₆ :IQ ₂₇ = 1:4.

IQ ₂₆ and FQ ₂₇ are currents flowing through transistors Q ₂₆ and Q ₂₇ . In this way, the transistor
The output video signals of Q ₂₅ and Q ₂₇ are maintained at V _D without saturation.
When _D1 = 8V, equal amplitude output of ±4Vpp can be obtained.

FIG. 6 shows a specific circuit example of the peak clamp circuit 13, the gate circuit 14, and the buffer circuit 15.
In Figure 6, C ₁ and C ₂ are coupling capacitors,
Resistors R ₁ and R ₂ and diodes D ₁ and D ₂ are bias circuits that determine the clamp level. transistor
Q ₁ is a clamping transistor that clamps the leading edge of the negative synchronizing signal to a voltage determined by the bias circuit, and transistor Q ₄ is a clamping transistor that clamps the positive synchronizing signal leading edge. Transistors Q ₂ , Q ₃ and Q ₅ , Q ₆ are emitter follower transistors. In the above configuration, the output of the bipolar video signal generation circuit 12 shown in FIG. 5 is added as an input signal. Positive video signals are applied through coupling capacitor _C1 , and negative video signals are applied through capacitor _C2 . Here, if the resistances R ₁ and R ₂ of the bias circuit are chosen equally, the base potential of the transistor Q ₁ is V _BQ1 = V _DD1 −2V _F /2R ₁ ×R ₁ +2V _F = V _DD1 /2 + V _F Therefore, the transistor Q ₁ The emitter potential of is V _BQ1 - V _F = V _DD1 /2 (where V _F is the base-emitter forward voltage of the diodes D ₁ and D ₂ or the transistor), and this becomes the clamp level of the positive input video signal ei, and the synchronizing signal is clamped at the tip of the The clamped video signal is taken out via the emitter follower transistors Q ₂ and Q ₃ , but in the case of a positive polarity video signal, the current path that charges the coupling capacitor C ₁ goes from the input end to the base of the transistor Q ₂ . Since this is the direction, normal clamping operation will not occur unless an NPN is used for transistor _Q2 as an emitter follower. Here, if only the emitter follower transistor Q ₂ is used, the output crank level V _E Q ₂ will be V _DD1 /2 - V _F , so it is corrected by the emitter follower of the PNP transistor Q ₃ , and the output clamp level is It is made to be V _DD1 /2 (=emitter potential V _E Q ₃ of Q ₃ ). In this way, the V _F term disappears, so V _F due to temperature change
Stable clamping operation can be obtained without being affected by drift.

Similarly, a video signal of negative polarity is input to the base of transistor _Q5 via _C2 .

To find the clamp level in this case, the base potential of transistor Q ₄ is V _BQ4 = V _DD1 - 2V _F /2R ₂ ×R ₂ = V _DD1 /
2-V _F and therefore the clamp level transistor Q ₄
The emitter potential of is V _BQ4 +V _F =V _DD1 /2.
The leading end (positive end) of the synchronizing signal of the input video signal is clamped at this level. At this time capacitor C ₂
Since the charging current is from the base of the transistor _Q5 toward the input terminal side, it is necessary to use a PNP for the emitter follower transistor _Q5 and use its base current as the charging current. Transistor Q ₅
The V _F of the transistor Q ₆ is canceled out by the V _F of the transistor Q 6 , and the clamp level at the output (=emitter potential of Q ₆ ) becomes V _DD1 /2.

Now, considering the case where the power supply voltage V _DD1 fluctuates, the clamp level is V _DD1 /2 as described above, so even if V _DD1 fluctuates, it always follows at a level of 1/2 of that. Therefore, the output video signal of the clamp circuit 13 can always be taken out as a signal of both positive and negative polarity clamped around V _DD1 /2.

Furthermore, considering the dynamic range, for example, if V _DD1 = 8 ^v , the clamp level is V _DD
1 /2=4V. Therefore, the input signal ei or maximum (at white peak) can be input up to 4Vpp, and after clamping, this input signal is saturated by a suitable combination of emitter follower transistors Q ₂ , Q ₃ and Q ₅ , Q ₆ It is taken out without any problem, and a dynamic range of 8Vpp can be obtained. These clamped video signals are processed by a gate pulse of a field period supplied from the outside by a gate circuit 14 composed of, for example, a CMOS bidirectional analog switch.
Positive and negative video signals are alternately gated and extracted for each field. When the gate pulse is at high level, transistors Q ₇ , Q ₈ , and Q ₁₂ turn on and output a positive video signal, and when the gate pulse is at low level, transistors Q ₉ , Q ₁₀ , and Q ₁₁ turn on.
Turn on and output a negative polarity video signal. Since such a gate circuit outputs an input signal with almost no DC loss, the clamp level of the clamp circuit 13 does not change even with the output of the gate circuit 14. The output of the gate circuit 14 is guided to a buffer amplifier 15 so as to be able to sufficiently drive the load circuit. The buffer amplifier 15 is a PNP emitter follower transistor to ensure a sufficiently wide dynamic range.
Q ₁₃ , resistor R ₈ , NPN constant current type emitter follower transistor Q ₁₄ , resistor R ₇ forming a constant current source, transistor Q ₁₅ and diode D ₃ , and the power supply of the first stage emitter follower is A higher V _DD2 than V _DD1 is used. With such a configuration, a video signal of a maximum of 8 Vpp (14 Vpp centered on V _DD1 /2) of the output of the gate circuit 14 can be output at low impedance without being saturated. Further, the clamp level can be maintained at V _DD1 /2. This is because the emitter follower transistors Q ₁₃ and Q ₁₄ cancel out the V _F term, making the circuit resistant to temperature drift.

If the video signal processing method described above is used,
Even if the power supply voltage V _DD1 fluctuates when a video signal (alternating video signal) with a waveform and DC level as shown in FIG. 3 is applied to an AC-driven liquid crystal, the potential of the common electrode 3 V _DD1 /2
It can be stably supplied mainly with , and has no temperature coefficient, so it is resistant to temperature changes. Furthermore, it has a wide dynamic range and can take out an alternating video signal that does not saturate from the ground to the power supply voltage.

Therefore, the video signal has no offset with respect to the common electrode potential (V _DD1 /2), and the liquid crystal can be driven with a video signal whose polarity is reversed for each field, so the life of the liquid crystal can be extended and the contrast can be improved. High-quality images can be played.

As described above, according to the present invention, the detected video signal is subjected to gamma correction in the first stage according to the gamma of the liquid crystal used, and then the video signal is converted into a video signal with a predetermined amplitude and both positive and negative polarities (equal amplitude). After that, each of the bipolar video signals is set to V _DD1 /2 at the tip of the synchronization signal using a _peak clamp circuit that is stable and has a wide dynamic range and is not affected by fluctuations in the power supply voltage V _DD1 or temperature drift in V F. Clamp and
By alternately gating positive and negative video signals for each field using a gate circuit and outputting them through a buffer amplifier with no temperature drift and a wide dynamic range, the system is resistant to power supply voltage fluctuations and temperature changes. It is possible to provide a video signal processing circuit that has the advantage of being able to drive video signals over a wide dynamic range from approximately ground to power supply voltage V _DD1 .

[Brief explanation of the drawing]

Figure 1 is a principle diagram of an AC drive type liquid crystal display, Figure 2 is an equivalent circuit diagram of an active matrix type LCD TV display panel, Figure 3 is a diagram showing the video signals supplied to an AC drive type liquid crystal display panel, FIG. 4 is a block diagram of a video signal processing circuit showing an embodiment of the present invention, FIG. 5 is a diagram showing a specific example of a part of the circuit shown in FIG. 4, and FIG. 6 is a diagram showing a specific circuit example of a part of the circuit shown in FIG. FIG. 3 is a diagram illustrating some specific circuit examples. 11... Gamma correction circuit, Q ₁ , Q ₄ ... Clamping transistor, 12... Bipolar video signal generation circuit,
Q ₂ , Q ₃ , Q ₅ , Q ₆ ... Emitter follower, 13 ... Peak clamp circuit, R ₁ , R ₂ ... Bias resistor, 1
4...Gate circuit, _D1 , _D2 ...Bias diode, 15...Buffer amplifier.

Claims (1)

[Scope of Claims] 1. A gamma correction circuit that performs gamma correction on a detected video signal in accordance with the display characteristics of a liquid crystal display element, and the output of this gamma correction circuit is supplied as an input, and a positive polarity signal with a predetermined amplitude is provided as an output. a signal generation circuit that generates a first video signal and a second video signal of negative polarity; a peak clamp circuit that clamps synchronization signal peak values of the first and second video signals to a predetermined level; A video signal processing circuit comprising a gate circuit and a buffer amplifier for alternately extracting clamped first and second video signals for each field, wherein the peak clamp circuit is connected in series between a voltage source and a reference potential point. connected first resistor, first, second
and a second resistor having the same value as the first resistor, the collector-emitter path is arranged between the voltage source and the first video signal supply line, and the base A clamping NPN connected to the connection point between the resistor and the first diode.
a clamping NPN transistor whose emitter-collector path is arranged between a second video signal supply line and a reference potential point, and whose base is connected to a connection point between the second resistor and the second diode; A first emitter follower that directly connects emitter follower transistors made of NPN and PNP, and guides the first video signal clamped by the clamping NPN transistor to the gate circuit, and an emitter follower made of PNP and NPN. A video signal processing circuit comprising a second emitter follower directly connected to a follower transistor and for guiding a second video signal clamped by the clamping PNP transistor to the gate circuit.