KR940017716A - Digital VRL's Synchronous Signal Detection Circuit - Google Patents

Digital VRL's Synchronous Signal Detection Circuit Download PDF

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Publication number
KR940017716A
KR940017716A KR1019920024717A KR920024717A KR940017716A KR 940017716 A KR940017716 A KR 940017716A KR 1019920024717 A KR1019920024717 A KR 1019920024717A KR 920024717 A KR920024717 A KR 920024717A KR 940017716 A KR940017716 A KR 940017716A
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South Korea
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signal
synchronization
output
unit
window
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KR1019920024717A
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Korean (ko)
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KR950014342B1 (en
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양태석
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이헌조
주식회사 금성사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/93—Regeneration of the television signal or of selected parts thereof

Abstract

본 발명은 디지탈 브이씨알의 동기신호 검출회로에 관한것으로, 종래에는 버스트 에러가 발생하면 클럭의 갯수가 데이타 갯수가 달라져 위도우 신호와 실제동기 패턴의 위치가 맞지않아 잘못된 데이타가 발생하는 문제점이 있었다.The present invention relates to a synchronization signal detecting circuit of a digital VRL. In the related art, when a burst error occurs, the number of clocks is changed, and thus the wrong data is generated because the position of the widow signal and the actual synchronization pattern do not match.

이러한 점을 감안하여 본 발명에서는 버스트 에러가 발생하면 윈도우 신호와 틀어진 동기검출 신호를 일정시간 계수하여 트랙중간에서 동기조정신호로 리세트시킴으로써 윈도우 신호와 동기패턴의 위치를 조정하여 정확한 데이타 및 동기신호를 검출할 수 있는 효과가 있다.In view of the above, in the present invention, when a burst error occurs, the window signal and the synchronization detection signal are counted for a predetermined time and reset to the synchronization adjustment signal in the middle of the track to adjust the position of the window signal and the synchronization pattern so that accurate data and synchronization signals There is an effect that can be detected.

Description

디지탈 브이 씨알의 동기신호 검출회로Digital V-Seal's Sync Signal Detection Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 4 도는 본 발명 디지탈 브이씨알의 동기신호 검출회로의 블럭도, 제 5 도는 제 4 도에 있어서, 버스트 에러 검출부의 상세 회로도, 제 6 도는 제 4 도에 있어서, 각부의 파형도.4 is a block diagram of a synchronous signal detection circuit of the present invention Digital VR, FIG. 5 is a detailed circuit diagram of a burst error detection section in FIG. 4, and FIG. 6 is a waveform diagram of each section in FIG.

Claims (6)

직렬클럭(SCLK)을 입력받아 병렬클럭(PCLK)을 발생시키는 클럭발생부(1)와, 이 클럭발생부(1)의 출력(PCLK)이 입력함에 따라 더미신호(DumH)를 발생시킨후 윈도우신호(Window) 및 강제동기(Csyn)를 발생시키는 신호제어부(3)와, 이 신호제어부(3)의 강제동기(Csyn)를 입력받아 직렬데이타(SD)에서 동기신호(Sync)를 검출하는 동기검출부(2)와, 상기 클럭발생부(1)의 출력(PCLK)에 따라 직렬데이타(SD)를 입력받아 상기 동기검출부(2)의 출력(Cync)에 동기된 병렬데이타(PD)를 출력하는 데이타변환부(4)와, 상기 클럭발생부(1)의 클럭(PCLK)에 따라 상기 동기검출부(2)의 출력(Sync) 및 데이타 변환부(4)의 출력(PD)을 조정하는 지연부(5)와, 상기 신호제어부(3)의 출력(Window) 및 동기검출부(2)의 동기검출신호(DS)를 입력받아 버스트 에리검출신호(BED)를 출력하는 버스트 에러검출부(10)와, 이 버스트 에러검출부(10)의 출력(BED) 및 상기 신호제어부(3)의 출력(Window)를 입력받아 상기 동기검출부(2)에 동기조정신호(Nwindow)를 출력하는 동기조정부(20)로 구성한 것을 특징으로 하는 디지탈 브이씨알의 동기신호 검출회로.The clock generator 1 receives the serial clock SCLK and generates the parallel clock PCLK, and generates a dummy signal DuH as the output PCLK of the clock generator 1 receives the window. Synchronization for detecting the synchronization signal Sync from the serial data SD by receiving the signal control unit 3 for generating the signal Window and the forced synchronization Csyn and the forced synchronization Csyn of the signal control unit 3. The detection unit 2 receives serial data SD according to the output PCLK of the clock generator 1, and outputs parallel data PD synchronized with the output Cync of the synchronization detection unit 2. A delay unit for adjusting the output (Sync) of the synchronization detector (2) and the output (PD) of the data converter (4) in accordance with the data converter (4) and the clock (PCLK) of the clock generator (1). (5), a burst error detection unit 10 which receives the output Window of the signal control unit 3 and the synchronization detection signal DS of the synchronization detection unit 2 and outputs a burst erasure detection signal BED; This The synchronization controller 20 is configured to receive an output BED of the burst error detection unit 10 and an output Window of the signal control unit 3 and output a synchronization adjustment signal Nwindow to the synchronization detection unit 2. A digital VCC synchronization signal detection circuit characterized by the above-mentioned. 제 1 항에 있어서, 버스트 에러검출부(10)는 윈도우신호(Window)와 동기검출신호(DS)를 논리조합하여 카운트클럭(CCLK)을발생시키는 카운터 클럭발생부(11)와, 동기조정신호(Nwindow)와 동기검출신호(DS), 더미신호(DumH)를 논리조합하여 크리어신호(Clr)를 출력하는 카운터 크리어부(12)와, 이 카운터크리어부(12)의 출력(Clr)에 따라 크리어되고 상기 카운터 클럭발생부(11)의 출력(CCLK)에 따라 계수하는 카운터(13)와, 이 카운터(13)의 출력(QD∼QA)을 논리조합하여 에러검출신호(BED)를 출력하는 에러검출신호출력부(14)로 구성한 것을 특징으로 하는 디지탈 브이씨알의 동기신호 검출회로.2. The burst error detection unit (10) according to claim 1, wherein the burst error detection unit (10) comprises a counter clock generator (11) for generating a count clock (CCLK) by logically combining the window signal (Window) and the synchronization detection signal (DS), and the synchronization adjustment signal ( The counter cree unit 12 outputs a cree signal Clr by logically combining the Nwindow, the synchronization detection signal DS, and the dummy signal DumH, and the cree according to the output Clr of the counter cree unit 12. And an error detection signal BED is output by logically combining the counter 13 that counts according to the output CCLK of the counter clock generator 11 and the outputs Q D to Q A of the counter 13. And an error detection signal output section (14). 제 2 항에 있어서, 카운터 클럭발생부(11)는 동기 검출신호(ds)를 반전시키는 인버터(IN1)의 출력(DS)이 일측 입력에 접속되고 타측입력에 윈도우신호(Window)가 접속되어 카운트 클럭(CCLK)을 발생시키는 앤드게이트(ANl)로 구성한 것을 특징으로 하는 디지탈 브이씨알의 동기신호 검출회로.The counter clock generator 11 has an output DS of the inverter IN 1 for inverting the synchronous detection signal ds, connected to one input and a window signal Window connected to the other input. A digital V-SR synchronization signal detecting circuit comprising an AND gate (AN 1 ) for generating a count clock (CCLK). 제 2 항에 있어서, 카운터 크리어부(12)는 동기검출신호(DS)가 일측 입력에 접속된 오아게이트(ORl)의 타측 입력에 동기조정신호(Nwindow)를 접속하고 그 오아게이트(OR1)의 출력이 일측 입력에 접속된 앤드게이트(AN2)의 타측 입력에 더미신호(DumH)를 접속하여 크리어신호(Clr)가 출력하도록 구성한 것을 특징으로 하는 디지탈 브이씨알의 동기신호 검출회로.The counter clear unit 12 is configured to connect the synchronization adjustment signal Nwindow to the other input of the OR gate OR l whose synchronization detection signal DS is connected to one input, and to the OR gate OR 1. And a dummy signal (DumH) connected to the other input of the AND gate (AN 2 ) whose output is connected to one input, so that the clear signal (Clr) is outputted. 제 2 항에 있어서, 에리검출신호출력부(14)는 카운터(13)의 출력(QA,QS,QD)을 반전시키는 인버터(IN2),(IN3),(IN4)의 출력및 상기 카운터(13)의 출력(Qc)이 입력단자에 접속된 낸드게이트(NA1)에 에러검출신호(BED)가 동기조정부(20) 및 신호제어부(3)에 출력되도록 구성된 것을 특징으로 하는 디지탈 브이씨알의 동기신호 검출회로.3. The inverter detection signal output unit 14 according to claim 2 is characterized in that the inverters IN 2 , IN 3 , and IN 4 which invert the outputs Q A , Q S , Q D of the counter 13. The error detection signal BED is output to the synchronization adjusting unit 20 and the signal control unit 3 at the NAND gate NA 1 connected to the output terminal and the output Qc of the counter 13. Digital VCC synchronization signal detection circuit. 제 1 항에 있어서, 동기조정부(20)는 윈도우신호(Window) 및 에러검출신호(BED)를 입력으로 하는 앤드게이트(AN3)에서 동기조정신호(Nwindow)를 발생시켜 동기검출부(2) 및 버스트 에리검출부(10)에 출력하도록 구성한 것을 특징으로 하는 디지탈 브이씨알의 동기신호 검출회로.2. The synchronization adjusting unit (20) according to claim 1, wherein the synchronization adjusting unit (20) generates a synchronization adjustment signal (Nwindow) at an AND gate (AN 3 ) that receives a window signal (Window) and an error detection signal (BED). A digital V-CAL synchronization signal detection circuit, configured to output to a burst erasure detecting unit (10). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920024717A 1992-12-17 1992-12-17 Synchronous signal detecting circuit KR950014342B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548223B1 (en) * 1998-07-03 2006-03-23 삼성전자주식회사 Burst Error Detection Device and Detection Method of Magnetic Recording & Reproducing Equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548223B1 (en) * 1998-07-03 2006-03-23 삼성전자주식회사 Burst Error Detection Device and Detection Method of Magnetic Recording & Reproducing Equipment

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