KR940016463A - Semiconductor integrated circuit device and manufacturing method - Google Patents

Semiconductor integrated circuit device and manufacturing method Download PDF

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KR940016463A
KR940016463A KR1019930025386A KR930025386A KR940016463A KR 940016463 A KR940016463 A KR 940016463A KR 1019930025386 A KR1019930025386 A KR 1019930025386A KR 930025386 A KR930025386 A KR 930025386A KR 940016463 A KR940016463 A KR 940016463A
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semiconductor
oxide film
silicon oxide
integrated circuit
circuit device
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KR1019930025386A
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미끼노리 가와지
히로따까 니시자와
요시아끼 아나따
노부오 단바
도시로 히라모또
다까히데 이와다
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가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/205Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

반도체집적회로장치 및 그 제조방법에 관한 것으로써, 양이온의 소자형성영역에 침입하는 것을 억제 또는 방지하기 위해, 실리콘으로 이루어지는 지지기판, 지지기판상에 제 1 실리콘산화막을 거쳐서 형성된 얇은 실리콘층, 얇은 실리콘층의 주면측에서 깊이방향으로 형성되고, 제 1 실리콘산화막에 도달하고, 실리콘층을 여거래의 반도체섬영역으로 분할하는 분할홈, 분할홈의 표면 또는 분리기판내에 형성된 제2 실리콘산화막, 여러개의 반도체섬영역의 주면에 마련된 여러개의 반도체능동소자, 상기 제 1 실리콘산화막과 제 2 실리콘산화막에 의해 형성된 산화막경로의 적어도 일부에 마련된 양이온확산방지수단을 구비한다.A semiconductor integrated circuit device and a method for manufacturing the same, comprising: a support substrate made of silicon, a thin silicon layer formed on a support substrate via a first silicon oxide film, to prevent or prevent intrusion into a device formation region of a cation; Split grooves formed in the depth direction on the main surface side of the silicon layer and reaching the first silicon oxide film and dividing the silicon layer into semiconductor island regions of the trade, second silicon oxide films formed on the surface of the divided grooves or in the separator substrate, And a plurality of semiconductor active elements provided on the main surface of the semiconductor island region of the semiconductor device, and cation diffusion preventing means provided on at least part of the oxide film path formed by the first silicon oxide film and the second silicon oxide film.

이러한 장치와 방법을 이용하는 것에 의해, 양이온이 소자형성영역에 침입하는 것을 방지할 수 있다.By using such an apparatus and method, it is possible to prevent cations from entering the device formation region.

Description

반도체집적회로장치 및 그 제조방법Semiconductor integrated circuit device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 제 1 실시예로써, 본 발명이 적용된 반도체집적회로장치의 주요부 단면도, 제 2 도는 제 1 도의 반도체집적회로장치가 패케이지기판상에 내장된 상태를 도시한 도면, 제 3 도 ~제13도는 제 1 도의 반도체집적회로장치를 제조하기 위한 프로세스를 공정순으로 도시한 도면.1 is a cross-sectional view of an essential part of a semiconductor integrated circuit device to which the present invention is applied, and FIG. 2 is a view showing a state in which the semiconductor integrated circuit device of FIG. 1 is embedded on a package board. 13 shows, in process order, the process for manufacturing the semiconductor integrated circuit device of FIG.

Claims (25)

반도체 기판, 상기 반도체기판의 표면상의 제 1 실리콘산화막, 상기 제 1 실리콘산화막의 표면상의 반도체층, 상기 반도체층의 표면에서 상기 제 1 실리콘산화막의 상기 표면으로 연장하여 상기 반도체층을 여러개의 반도체영역으로 분리하는 홈, 상기 홈의 측면상의 제 2 실리콘산화막, 상기 여러개의 반도체섬영역의 주면상에 형성된 반도체소자 및 상기 제 1 산화막실리콘막과 상기 제 2 실리콘산화막사이에 형성된 질화실리콘 막을 포함하는 반도체집적회로장치.A semiconductor substrate, a first silicon oxide film on the surface of the semiconductor substrate, a semiconductor layer on the surface of the first silicon oxide film, and extending from the surface of the semiconductor layer to the surface of the first silicon oxide film to extend the semiconductor layer into a plurality of semiconductor regions. A semiconductor comprising a groove separated by a semiconductor layer, a second silicon oxide film on the side surface of the groove, a semiconductor element formed on a main surface of the plurality of semiconductor island regions, and a silicon nitride film formed between the first silicon oxide film and the second silicon oxide film. Integrated circuit device. 제 1 항에 있어서, 상기 질화실리콘막은 상기 제 1 실리콘산화막의 표면 전체를 피복하는 반도체집적회로장치.The semiconductor integrated circuit device according to claim 1, wherein said silicon nitride film covers the entire surface of said first silicon oxide film. 제 1 항에 있어서, 상기 반도체기판과 상기 반도체층의 각각은 단결정실리콘인 반도체집적회로장치.The semiconductor integrated circuit device according to claim 1, wherein each of the semiconductor substrate and the semiconductor layer is single crystal silicon. 제 1 항에 있어서, 상기 제 2 실리콘산화막과 함께 상기 홈은 상기 여러개의 반도체 소자의 각각을 격리하는 격리구조를 형성하는 반도체집적회로장치.2. The semiconductor integrated circuit device according to claim 1, wherein said groove together with said second silicon oxide film forms an isolation structure that isolates each of said plurality of semiconductor elements. 제 4 항에 있어서, 상기 여러개의 반도체소자는 MOSFET를 포함하는 반도체집적회로장치.5. The semiconductor integrated circuit device according to claim 4, wherein said plurality of semiconductor devices comprise MOSFETs. 반도체 기판, 상기 반도체기판의 표면상의 제 1 실리콘산화막, 상기 제 1 실리콘산화막의 표면상의 반도체층, 상기 반도체층의 표면에서 상기 제 1 실리콘산화막의 표면으로 연장하여 상기 반도체층을 여러개의 반도체섬영역으로 분리하는 홈, 상기 홈의 측면상의 제 2 실리콘산화막 및 상기 여러개의 반도체섬영역의 주면상에 형성된 반도체소자를 포함하며, 상기 제 2 실리콘산화막과 함께 상기 홈은 상기 여러개의 반도체소자를 포함하며, 상기 제 2 실리콘산화막과 함께 상기 홈은 상기 여러개의 반도체소자의 각각을 격리하는 격리구조를 형성하고, 상기 격리구조 아래에위치한 상기 제 1 실리콘산화막은 인으로 도프된 반도체집적회로장치.A semiconductor substrate, a first silicon oxide film on the surface of the semiconductor substrate, a semiconductor layer on the surface of the first silicon oxide film, and extending from the surface of the semiconductor layer to the surface of the first silicon oxide film to extend the semiconductor layer into a plurality of semiconductor island regions. And a semiconductor device formed on a main surface of the plurality of semiconductor island regions and a second silicon oxide film on the side of the groove, wherein the groove together with the second silicon oxide film includes the plurality of semiconductor devices. And the groove together with the second silicon oxide film form an isolation structure for isolating each of the plurality of semiconductor devices, wherein the first silicon oxide film under the isolation structure is doped with phosphorus. 제 6 항에 있어서, 상기 제 1 실리콘산화막은 전체적으로 인으로 도프된 반도체집적회로장치.7. The semiconductor integrated circuit device according to claim 6, wherein the first silicon oxide film is entirely doped with phosphorus. 제 6 항에 있어서, 상기 반도체기판과 상기 반도체층의 각각은 단결정실리콘인 반도체집적회로장치.7. The semiconductor integrated circuit device according to claim 6, wherein each of the semiconductor substrate and the semiconductor layer is single crystal silicon. 제 6 항에 있어서, 상기 여러개의 반도체소자는 MOSFET를 포함하는 반도체집적회로장치.7. The semiconductor integrated circuit device according to claim 6, wherein said plurality of semiconductor devices comprise MOSFETs. 반도체기판, 상기 반도체기판의 표면상의 제 1 실리콘산화막, 상기 제 1 실리콘산화막의 표면상의 반도체층, 상기 반도체층의 표면에서 상기 제 1 실리콘산화막의 상기 표면으로 연장하여 상기 반도체층을 여러개의 반도체섬영역으로 분리하는 홈, 상기 홈의 측면상의 제 2 실리콘산화막, 인으로 도프되고 상기 홈내에 충전된 다결정실리콘 및 상기 여러개의 반도체섬영역의 주면상에 형성된 반도체소자를 포함하며, 상기 다결정실리콘 및 상기 제 2 실리콘산화막과 함께 상기 홈은 상기 여러개의 반도체소자의 각각을 격리하는 격리구조를 형성하는 반도체집적회로장치.A semiconductor substrate, a first silicon oxide film on the surface of the semiconductor substrate, a semiconductor layer on the surface of the first silicon oxide film, and extending from the surface of the semiconductor layer to the surface of the first silicon oxide film to extend the semiconductor layer into a plurality of semiconductor islands. A polysilicon doped with a region, a second silicon oxide film on the side of the groove, polycrystalline silicon doped with phosphorus and filled in the groove, and a semiconductor element formed on a main surface of the plurality of semiconductor island regions, wherein the polycrystalline silicon and the And the groove together with the second silicon oxide film form an isolation structure that isolates each of the plurality of semiconductor devices. 제10항에 있어서, 상기 반도체기판과 상기 반도체층의 각각은 단결정실리콘인 반도체집적회로장치.The semiconductor integrated circuit device according to claim 10, wherein each of the semiconductor substrate and the semiconductor layer is single crystal silicon. 제10항에 있어서, 상기 여러개의 반도체소자는 MOSFET를 포함하는 반도체집적회로장치.The semiconductor integrated circuit device according to claim 10, wherein the plurality of semiconductor devices comprise MOSFETs. 반도체기판, 상기 반도체기판의 표면상의 제 1 실리콘산화막, 상기 제 1 실리콘산화막의 표면상의 반도체층, 평면에서 봐서 상기 반도체층의 제 1 영역을 둘러싸도록 상기 반도체층의 바깥둘레에 형성되어 상기 반도체층의 표면에서 상기 제 1 실리콘산화막으로 연장하는 제 1 홈, 상기 반도체층의 상기 제 1 영역에 형성되고, 상기 반도체층의 상기 표면에서 상기 제 1 실리콘산화막의 상기 표면으로 연장하여 상기 반도체층의 상기 제 1 영역을 여러개의 반도체섬영역으로 분리하는 제 2 홈, 상기 홈의 측면상의 제 2 실리콘산화막 및 상기 여러개의 반도체섬영역의 주면상에 형성된 반도체소자를 포함하며, 상기 제 2 실리콘산화막과 함께 홈은 상기 여러개의 반도체소자의 각각을 격리하는 격리구조를 형성하고, 상기 격리구조의 아래에 위치한 상기 제 1 실리콘산화막은 인으로 도프된 반도체집적회로장치.A semiconductor substrate, a first silicon oxide film on the surface of the semiconductor substrate, a semiconductor layer on the surface of the first silicon oxide film, and formed on an outer circumference of the semiconductor layer so as to surround the first region of the semiconductor layer in plan view; A first groove extending from the surface of the semiconductor layer to the first silicon oxide film, the first region of the semiconductor layer, extending from the surface of the semiconductor layer to the surface of the first silicon oxide film, A second groove that separates the first region into a plurality of semiconductor island regions, a second silicon oxide film on the side surface of the groove, and a semiconductor element formed on a main surface of the plurality of semiconductor island regions, together with the second silicon oxide film. The groove forms an isolation structure that insulates each of the plurality of semiconductor elements, and the first structure is located below the isolation structure. The silicon oxide film is doped with a semiconductor integrated circuit device. 제13항에 있어서, 상기 제 1 실리콘산화막은 전체적으로 인으로 도프된 반도체집적회로장치.The semiconductor integrated circuit device according to claim 13, wherein the first silicon oxide film is entirely doped with phosphorus. 제13항에 있어서, 상기 반도체기판과 상기 반도체층의 각각은 단결정실리콘인 반도체집적회로장치.The semiconductor integrated circuit device according to claim 13, wherein each of the semiconductor substrate and the semiconductor layer is single crystal silicon. 제13항에 있어서, 상기 여러개의 반도체소자는 MOSFET를 포함하는 반도체집적회로장치.The semiconductor integrated circuit device according to claim 13, wherein the plurality of semiconductor devices comprise MOSFETs. 제1항에 있어서, 상기 여러개의 반도체소자는 바이폴라 트랜지스터를 포함하는 반도체집적회로장치.The semiconductor integrated circuit device of claim 1, wherein the plurality of semiconductor devices comprise bipolar transistors. 제6항에 있어서, 상기 여러개의 반도체소자는 바이폴라 트랜지스터를 포함하는 반도체집적회로장치.7. The semiconductor integrated circuit device according to claim 6, wherein the plurality of semiconductor devices comprise bipolar transistors. 제10항에 있어서, 상기 여러개의 반도체소자는 바이폴라 트랜지스터를 포함하는 반도체집적회로장치.The semiconductor integrated circuit device of claim 10, wherein the plurality of semiconductor devices comprise bipolar transistors. 제13항에 있어서, 상기 여러개의 반도체소자는 바이폴라 트랜지스터를 포함하는 반도체집적회로장치.The semiconductor integrated circuit device of claim 13, wherein the plurality of semiconductor devices comprise bipolar transistors. 제 1 항에 있어서, 상기 여러개의 반도체소자는 MOSFET 및 바이폴라 트랜지스터를 포함하는 반도체집적회로장치.The semiconductor integrated circuit device of claim 1, wherein the plurality of semiconductor devices include a MOSFET and a bipolar transistor. 제 6 항에 있어서, 상기 여러개의 반도체소자는 MOSFET 및 바이폴라 트랜지스터를 포함하는 반도체집적회로장치.7. The semiconductor integrated circuit device according to claim 6, wherein the plurality of semiconductor devices comprise MOSFETs and bipolar transistors. 제10항에 있어서, 상기 여러개의 반도체소자는 MOSFET 및 바이폴라 트랜지스터를 포함하는 반도체집적회로장치.11. The semiconductor integrated circuit device according to claim 10, wherein the plurality of semiconductor devices comprise MOSFETs and bipolar transistors. 제13항에 있어서, 상기 여러개의 반도체소자는 MOSFET 및 바이폴라 트랜지스터를 포함하는 반도체집적회로장치.The semiconductor integrated circuit device of claim 13, wherein the plurality of semiconductor devices comprise MOSFETs and bipolar transistors. 반도체기판, 상기 반도체기판의 표면상의 제 1 실리콘산화막, 상기 제 1 실리콘산화막의 표면상의 질화실리콘막 및 상기 질화실리콘막의 표면상의 반도체층을 갖는 반도체본체를 준비하는 스텝, 상기 반도체층을 여러개의 반도체섬영역으로 분리하기 위해 상기 반도체층의 표면에서 상기 제 1 실리콘산화막의 상기 표면으로 연장하는 홈을 형성하는 스텝, 상기 홈의 측면상에 제 2 실리콘산화막을 형성하는 스텝 및 상기 여러개의 반도체섬영역의 주면상에 반도체소자를 형성하는 스텝을 포함하는 반도체집적회로장치의 제조방법.Preparing a semiconductor body having a semiconductor substrate, a first silicon oxide film on the surface of the semiconductor substrate, a silicon nitride film on the surface of the first silicon oxide film, and a semiconductor layer on the surface of the silicon nitride film; Forming a groove extending from the surface of the semiconductor layer to the surface of the first silicon oxide film to be separated into an island region, forming a second silicon oxide film on the side surface of the groove and the plurality of semiconductor island regions. A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming a semiconductor element on a main surface of the same. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930025386A 1992-12-02 1993-11-26 Semiconductor integrated circuit device and manufacturing method KR940016463A (en)

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JP4322185A JPH06177233A (en) 1992-12-02 1992-12-02 Semiconductor integrated circuit device and manufacture thereof

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