KR940016254A - High speed loo decoder - Google Patents

High speed loo decoder Download PDF

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Publication number
KR940016254A
KR940016254A KR1019920027040A KR920027040A KR940016254A KR 940016254 A KR940016254 A KR 940016254A KR 1019920027040 A KR1019920027040 A KR 1019920027040A KR 920027040 A KR920027040 A KR 920027040A KR 940016254 A KR940016254 A KR 940016254A
Authority
KR
South Korea
Prior art keywords
decoder
word line
driver
line driver
operated
Prior art date
Application number
KR1019920027040A
Other languages
Korean (ko)
Other versions
KR960001861B1 (en
Inventor
김정필
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920027040A priority Critical patent/KR960001861B1/en
Publication of KR940016254A publication Critical patent/KR940016254A/en
Application granted granted Critical
Publication of KR960001861B1 publication Critical patent/KR960001861B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)

Abstract

본 발명에서는 반도체 메모리 소자의 X-프리디코더에서의 지연시간을 줄이고, X- 디코더의 PMOS형 워드라인 드라이버의 전류 구동 능력을 향상시키기 위하여, 상기의 X-프리디코더를 제거하고 4개의 AXO1 어드레스 조합을 X-디코더에 첨가함으로써, X-디코더내의 4개의 PMOS형 워드라인 드라이버중 단지 한개만 선택된 AX01 어드레스에 의해 턴-온되도록 하여 동작 속도를 높이고, 상기의 PMOS형 워드라인 드라이버의 게이트, 소오스간 전위차를 고전압 Vpp레벨까지 높여서 전류 구동 능력을 향상시킨 고속 X-디코더 회로에 관한 기술이다.In the present invention, in order to reduce the delay time in the X-predecoder of the semiconductor memory device and improve the current driving capability of the PMOS type word line driver of the X-decoder, the X-predecoder is removed and four AXO1 address combinations are used. Is added to the X-decoder, allowing only one of the four PMOS-type wordline drivers in the X-decoder to be turned on by the selected AX01 address, speeding up the operation speed, and increasing the gate-to-source This technology relates to a high-speed X-decoder circuit that improves the current driving capability by raising the potential difference to the high voltage Vpp level.

Description

고속의 로오 디코더High speed loo decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 X-디코더의 실시예를 도시한 상세도, 제4도는 본 발명의 X-디코더에 관련된 신호의 파형도.3 is a detailed diagram showing an embodiment of the X-decoder of the present invention, and FIG. 4 is a waveform diagram of a signal related to the X-decoder of the present invention.

Claims (3)

반도체 메모리의 소자의 메모리 블럭내의 워드라인을 구동하는데 사용되는 X-디코더의 PMOS형 워드라인 드라이버는, 소오스단을 높은 전압 Vpp에 직접 연결되고, 드레인단은 워드라인에 연결되며, 게이트단은 한 메모리 블럭내의 워드라인 선택시에 사용되는 모든 어드레스 (AX01,23,45,67)에 의해 제어되는 트랜지스터인 것을 특징으로 하는 X-디코더.The X-decoder PMOS type word line driver used to drive the word lines in the memory block of a device of a semiconductor memory has a source end connected directly to a high voltage Vpp, a drain end connected to a word line, and a gate end connected to a word line driver. An X-decoder characterized by a transistor controlled by all addresses (AX01, 23, 45, 67) used in selecting a word line in a memory block. 제1항에 있어서, PMOS형 워드라인 드라이버가 동작되기전에, 상기 드라이버의 소오스단에 이미 고전압 Vpp레벨이 인가되는 것을 특징으로 하는 X-디코더.The X-decoder according to claim 1, wherein a high voltage Vpp level is already applied to a source terminal of the driver before the PMOS type word line driver is operated. 제1항에 있어서, PMOS형 워드라인 드라이버의 소오스단은 상기의 드라이버가 동작되기 전에는 Vcc레벨을 유지하다가, 상기의 드라이버가 동작된 후 Vcc레벨에서 Vpp레벨로 전이되는 것을 특징으로 하는 X-디코더.The X-decoder of claim 1, wherein the source terminal of the PMOS type word line driver maintains the Vcc level before the driver is operated, and then transitions from the Vcc level to the Vpp level after the driver is operated. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027040A 1992-12-31 1992-12-31 High speed row decoder KR960001861B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027040A KR960001861B1 (en) 1992-12-31 1992-12-31 High speed row decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027040A KR960001861B1 (en) 1992-12-31 1992-12-31 High speed row decoder

Publications (2)

Publication Number Publication Date
KR940016254A true KR940016254A (en) 1994-07-22
KR960001861B1 KR960001861B1 (en) 1996-02-06

Family

ID=19348187

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027040A KR960001861B1 (en) 1992-12-31 1992-12-31 High speed row decoder

Country Status (1)

Country Link
KR (1) KR960001861B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100516735B1 (en) * 2001-12-08 2005-09-22 주식회사 하이닉스반도체 Row access information transmit device using internal wiring of memory cell array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100516735B1 (en) * 2001-12-08 2005-09-22 주식회사 하이닉스반도체 Row access information transmit device using internal wiring of memory cell array

Also Published As

Publication number Publication date
KR960001861B1 (en) 1996-02-06

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