KR940013119A

KR940013119A - Mode Conversion Circuit of Image Processing Apparatus and Method

Info

Publication number: KR940013119A
Application number: KR1019920021308A
Authority: KR
Inventors: 박정일
Original assignee: 정용문; 삼성전자 주식회사
Priority date: 1992-11-13
Filing date: 1992-11-13
Publication date: 1994-06-25
Also published as: KR100201279B1

Abstract

화상처리장치의 모드변환을 위해 제안된 회로는 노말모드로 수신되는 화질신호의 데이타 및 상기 데이타의 변화처리된 데이타를 저장하는 저장수단과, 상기 저장수단으로 부터인가 되는 상기 병렬형태의 수신데이타를 직렬 데이타로 변환하는 병직렬 변환 수단과, 상기 직렬데이타를 수신하여 기, 우수 라인용 직렬데이타로 변환하는 변환 로직과, 상기 변환 로직의 상기 기, 우수 직렬 데이타를 적어도 하나 이상의 라인용 병렬데이타로 변환하여 적어도 하나 이상의 라인용 병렬데이타로 변환하여 상기 저장수단에 공급하는 직병렬 변환수단을 포함한다.A circuit proposed for mode conversion of an image processing apparatus includes a storage means for storing data of an image quality signal received in the normal mode and the processed data of the data, and a parallel reception data applied from the storage means. Parallel-to-serial conversion means for converting the data, conversion logic for receiving the serial data and converting the serial data into the even and even line serial data, and converting the basic and even serial data of the conversion logic into at least one parallel data for the line. And serial-to-parallel conversion means for converting the at least one parallel data for the line into the storage means.

본 발명에 따르면, 화질의 열화를 개선할 수 있음은 물론 전송 속도도 노말모드에 비해 향상된다.According to the present invention, the deterioration of the image quality can be improved and the transmission speed is also improved compared to the normal mode.

Description

Mode Conversion Circuit of Image Processing Apparatus and Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 모드변환 회로의 블럭도,3 is a block diagram of a mode conversion circuit of the present invention;

제4도는 제3도중 램(10)의 메모리 맵도,4 is a memory map diagram of the RAM 10 of FIG.

제5도는 제3도중 PSC(2,3,4)의 상세회로도,5 is a detailed circuit diagram of the PSC (2, 3, 4) in FIG.

제6도는 제3도중 변환로직부(20)의 상세회로도,6 is a detailed circuit diagram of the conversion logic unit 20 in FIG.

제7도는 제6도의 구체 회로도,7 is a detailed circuit diagram of FIG.

제8도는 제3도중 SPC(30,31)의 상세회로도.8 is a detailed circuit diagram of the SPC (30, 31) of the third.

Claims

A mode conversion circuit of an image processing apparatus, comprising: storage means for storing data of an image quality signal received in a normal mode and converted data of the data, and serial data of the parallel data received from the storage means; Parallel-to-serial conversion means for converting the?, The conversion logic for receiving the serial data and converting the serial data into the even and even line serial data, and converting the basic and even serial data of the conversion logic into at least one parallel data for the line; And serial-to-parallel conversion means for converting at least one parallel data for a line into the storage means.

The circuit according to claim 1, wherein the parallel data of said serial-to-parallel conversion means is data for three lines.

A mode conversion method of an image processing apparatus, the method comprising: storing data of a video signal received in a normal mode and converted data of the data; converting the parallel reception data into serial data; And converting serial data for even lines into at least one parallel data for lines.

※ Note: The disclosure is based on the initial application.