KR100201279B1 - Mode change circuit and its method for image processing device - Google Patents

Abstract

A circuit proposed for mode conversion of an image processing apparatus includes storage means for storing data of an image quality signal received in a normal mode and processed data of the data;

Parallel-to-serial conversion means for converting the parallel data received from the storage means into serial data;

A conversion logic for receiving the serial data and converting the serial data into serial data for good and even lines;

And serial-to-parallel conversion means for converting the basic and even serial data of the conversion logic into at least one or more line parallel data, and converting the at least one or more line parallel data to the storage means.

According to the present invention, the deterioration of the image quality can be improved and the transmission speed is also improved compared to the normal mode.

Description

Mode Conversion Circuit of Image Processing Apparatus and Method

1 is a diagram illustrating a connection between a typical facsimile system.

2 is a conversion output form of Hangul characters according to the conventional mode conversion.

3 is a block diagram of a mode conversion circuit of the present invention.

4 is a memory map diagram of the RAM 10 of FIG.

5 is a detailed circuit diagram of the PSCs (2, 3, 4) in FIG.

6 is a detailed circuit diagram of the conversion logic unit 20 in FIG.

7 is a detailed circuit diagram of FIG.

8 is a detailed circuit diagram of the SPC (30, 31) of the third.

The present invention relates to a mode conversion circuit of an image processing apparatus and a method thereof.

In general, an image processing apparatus such as a facsimile apparatus includes a fine mode and a normal mode.

The facsimile used as the image processing apparatus has two types of resolutions of 3.85line / mm ± 1% and 7.7line / mm ± 1% in the vertical direction as recommended in CCITT T.4. The 3.85 line is normally called a normal mode and the 7.7 line is called a fine mode. When a high resolution is not required as in a general document, the normal mode is used. When a high resolution is required, the normal mode is transmitted, but in this case, a transmission time is required.

Here, if there is a technique for converting the data transmitted in the normal mode to the fine mode it can be seen that it is very useful.

Fig. 1 is a diagram illustrating the connection between the general facsimile systems. In FIG. 1, the transmission fax 100 is connected to the reception fax 101 through a telephone line, and each has a fine and normal mode selection switch. In order to transmit high quality data, both the transmission and reception faxes 100 and 101 should be selected as the fine mode. In this case, the incoming fax is automatically received in the fine mode when the sender informs the user of the fine mode by the protocol. In addition, when high image quality is not required, it transmits and receives as the normal mode.

FIG. 2 shows an example of text data transmitted and received by the conventional mode selection technique as described above.

(A) of FIG. 2 shows the structure of the subcharacter in fine mode, and (2b) shows the structure of the subcharacter in normal mode.

The first line of the normal mode is vertically enlarged about twice the first line of the fine mode, and the second line of the normal mode of (2b) is vertically enlarged twice the third three of the fine mode. The third line of the normal mode is enlarged to twice the vertical of the fifth line of the fine mode.

Here, when the characters are small, it can be seen that the image quality is further degraded in the normal mode.

Therefore, in the related art, reception quality deteriorates when a small character is transmitted in a normal mode, and a long time is required when it is transmitted in a fine mode.

It is therefore an object of the present invention to provide an apparatus and method thereof which can solve the above-mentioned conventional problems.

Another object of the present invention is to provide an apparatus and method capable of increasing transmission speed while improving deterioration of image quality.

According to the present invention for achieving the above objects,

Storage means for storing the data of the image quality signal received in the normal mode and the converted data of the data;

Parallel and serial conversion means for converting the parallel data received from the storage means into serial data;

A conversion logic for receiving the serial data and converting the serial data into serial data for good and even lines;

And serial-to-parallel conversion means for converting the basic and even serial data of the conversion logic into at least one or more line parallel data, and converting the at least one or more line parallel data into the at least one line parallel data.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the following description, specific details will be set forth in order to provide a more complete understanding of the present invention. It will be apparent to those skilled in the art that the above description may be made and sufficient without the detailed description. In addition, well-known circuits and their functions are descriptive in order not to obscure the present invention.

3 is a block diagram of a mode conversion circuit of the present invention.

A RAM 10 for storing data received in a normal mode and storing the converted data of the data, and a first-3PSC (2, for converting the received data applied from the RAM 10 into serial data; 3,4),

A conversion logic unit 20 for receiving the serial data and converting the serial data into excellent serial data;

The conversion logic unit 20 is composed of first, second, and SPCs 30 and 31 for converting the excellent and excellent serial data into parallel data and supplying them to the RAM 10. The RAM 10 is divided into two parts for storing the received data and the processed data as shown in FIG.

In FIG. 3, the RAM 10 outputs reception data to the output terminal DOUT, and receives data of processing missing data from the reception terminal DIN.

The first to third PSC (Parallel to serial Conversion) converts the received data received from the RAM 10 into serial data and provides it to the conversion logic unit 20.

The detailed configuration of the 1-3PSCs (2, 3, 4) is shown in FIG.

5 is configured as flip-flops 200-203, inverters 213 and 214, and gate elements 205-212 to form one of the first to third PSCs 2, 3 and 4.

In FIG. 5, when the input stage LDB is low, the data is delayed and output according to the data input applied to each of the D-type flip-flops 200-203, and the (LDB) is high and there is a clock CK. In this case, it can be seen that serial data is output to the output terminal Sout by shifting.

The conversion logic unit 20 is constituted by the window unit 21 and the combinational logic unit 20 of FIG. 6 to output odd and even data.

The detailed configuration of the window portion 21 is comprised of flip-flops D1-D9 as shown in FIG. 7A, and the detailed configuration of the combinational logic unit 22 is shown in FIG. 7B.

Here, the window section 21 converts three lines of data received in series into 3x3 window data and provides a total of nine pieces of data to the combinational logic section 22.

The combinational logic unit 22 outputs the nine data as the data for the even line.

Each configuration of the 1-2SPCs 30 and 31 in FIG. 3 is shown in FIG.

In order to output parallel data of three lines of FIG. 8, four flip-flops DF1 to DF4 are configured.

After being stored in the processing result storage area of the RAM 10 provided as the parallel data, it is usually thermally recorded as a signal.

Therefore, according to the embodiment of the present invention, transmission of normalized signal data in normal mode can be received as in the conventional fine mode, so that the processing speed and resolution are improved.

As described above, the present invention has been illustrated according to the drawings and described in accordance with the embodiments, but the present invention is not limited thereto, and various changes and modifications can be made without departing from the basic definition of the present invention. Anyone with ordinary knowledge will know it clearly.

For example, although the structure of the said window part was made into 3x3, it can expand to more than that.

Claims (3)

A mode conversion circuit of an image processing apparatus, comprising: storage means for storing data of an image quality signal received in a normal mode and converted data of the data, and serial data for receiving the parallel data received from the storage means; Parallel-to-serial conversion means for converting the?, The conversion logic for receiving the serial data and converting the serial data into the even and even line serial data, and converting the basic and even serial data of the conversion logic into at least one parallel data for the line; And serial-to-parallel conversion means for converting at least one parallel data for a line into the storage means. The circuit according to claim 1, wherein the parallel data of said serial-to-parallel conversion means is data for three lines. A mode conversion method of an image processing apparatus, the method comprising: storing data of video signals received in a normal mode and converted data of the data; converting the parallel reception data into serial data; And converting the data into the serial data for the even lines, and converting the serial and even line serial data into at least one parallel data for the lines.