KR940011042B1 - Memory unit using banking program - Google Patents

Abstract

The memory device executes a large program with small memory by dividing programs and recording them in several ROMs, saving necessary program to RAMs and directly accessing program from ROM. The device comprises (A) ROM (10) saving banking program and module program; (B) ROM choice controller (20) and RAM (30) transferred from ROM program; (C) RAM output controller (40); (D) buffer (50).

Description

Memory device using banking program.

1 is a conventional memory configuration diagram.

2 is a detailed circuit diagram of the present invention.

3 is a memory diagram of the present invention.

4 is a flow chart of the present invention

* Explanation of symbols for main parts of the drawings

10: ROM 20: ROM selection control unit

30: ram 40: ram output control unit

50: buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device of a computer, and more particularly, to an apparatus capable of efficiently using a RAM area by selecting a corresponding ROM when necessary using a banking program and executing a program.

In general, the program stored in the ROM has been written to the RAM when the program is executed due to the characteristics of a read only memory (ROM) and a random access memory (RAM).

That is, as shown in FIG. 1, the central processing unit (hereinafter referred to as CPU) reads the program of the ROM, writes it to the corresponding address of the RAM, and executes all programs in the RAM.

However, as in the first diagram, when the address of ROM and RAM is overlapped, the program of ROM becomes smaller and the area of RAM that user can use is relatively small. In the extreme, if the program of ROM is larger than RAM, the program cannot be executed There was a problem with getting lost. Accordingly, an object of the present invention is to provide a memory device capable of executing a program by providing an appropriate user area even if a program of a ROM grows using a banking program.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a detailed logic diagram of the present invention, which includes a first ROM 11 and a second ROM 12 that store a banking program and a module program, and a ROM 10 and a no-gate G ₁ . A ROM selection control unit 20 composed of an oragate G ₂ -G ₃ and a latch F ₁ to selectively control the output of the ROM 10 by the control of a CPU (not shown); After the program of the ROM 10 is recorded, the RAM 30 is configured to execute the corresponding program, and the NAND gate G ₄ and the OA gate G ₅ -G ₆ are configured to input the output of the ROM selection controller 20. After the logical combination, the RAM output control unit 40 for outputting the output control signal of the RAM 30, the output of the RAM 30 is input and buffered by a predetermined output of the RAM output control unit 40 3 is a block diagram of a memory according to the present invention, and FIG. 4 is a flowchart according to the present invention. The.

Based on the above configuration, the present invention will be described in detail with reference to FIGS.

In FIG. 2, the CPU and the data and address buses of the CPU are not shown. In the first ROM 11, there is a jump table, and each jump routine records a module-programmed program. It is assumed that a general program is recorded in the second ROM 12 and a banking program is recorded in the first ROM 11.

신호와 상기 래치(F₁)의 신호이므로 초기에 앤드게이트(G₂)는 "로우"신호를 출력하여 제 1 롬(11)을 선택한다.When power is initially (Power on) the reset signal is input to the latch (F ₁₎ the latch (F ₁₎ that is clear and outputs a "low" signal. The input of the AND gate G ₂ is a predetermined address and read output from the CPU.

The AND gate G ₂ initially selects the first ROM 11 by outputting a "low" signal since it is a signal and a signal of the latch F ₁ .

를 인가하면 래치(F₁)가 "하이"신호로 천이되어 제 1 롬(11)을 오프시키고 CPU의 소정 어드레스 신호와 리드

신호를 입력하고 있는 오아게이트(G₃)에 제 2 롬(12)의 제어신호인 "로우"신호를 인가하면 오아게이트(G₃)의 출력은 "로우"신호가 도어 제 2 롬(20)이 선택되며 메모리 요구 신호

와 리드 신호

에 의해 제 2 롬(12)의 프로그램 데이타를 리드하여 램(30)의 해당 어드레스 라이트 시킨다.aAt this time, when the program data of the first ROM 11 and the second ROM 12 is written to the RAM 30 as shown in the third diagram, the program data of the second ROM 12 is first loaded into the RAM 30. do. That is, a "low" signal to the preset terminal of the latch (F ₁ )

When latch is applied, the latch F ₁ transitions to the "high" signal to turn off the first ROM 11 and read the predetermined address signal of the CPU.

If a "low" signal is the control signal of the second ROM 12 to the Iowa gate (G _3), which input signals applied Iowa output of the gate (G ₃₎ is "low" signal of the door second ROM 20 Is selected and the memory request signal

And lead signal

The program data of the second ROM 12 is read out so that the corresponding address of the RAM 30 is written.

Secondly, the program data of the first ROM 11 is loaded into the RAM 30. When the movement of the second ROM 12 is completed, the control signal of the second ROM 20 is set to "high" and the oragate ( The second ROM 12 is turned off by transitioning the output of G ₃ ) to a "high" signal.

In addition to the clock terminal of the first ROM by loading an on-signal is "low" signal on the input to the NOR gate (G _1), NOR gate (G ₁₎ of 11 is shifted to the "high" signal latch (F ₁₎ The latch F ₁ is applied by the "high" output of the nodal gate G ₁ to chip enable the first ROM 11 under the latch output and then the required first ROM ( The program of 11) is transferred to the address of the corresponding RAM 30. (B) After this process, the banking program is also transferred to the required portion of the RAM 30 in the same manner as described above. (All)

After completing the above-mentioned process (a) (b) (c), the first ROM 11 and the second ROM 12 are turned off, and the data stored in the RAM 30 is read or written. Perform.

That is, when the first ROM 11 and the second ROM 12 are turned off, since the two inputs of the NAND gate G ₄ are the “high” signals, the output of the NAND gate G ₄ becomes the “low” signal, and thus the RAM ( Since the output of 40 is applied to the enable signal of the buffer 50, the data of the RAM 30 is output by the read and memory request signals of the CPU.

When a program of the first ROM 11 is required when the program of the RAM 40 is executed, the program currently being executed is stored in a register of the CPU and the first ROM 10 is turned on.

Therefore, since the output of the latch F ₁ becomes a "low" signal and the oragate G ₂ also becomes a "low" signal, the first ROM 11 is chip-enabled and the NAND gate G ₄ is a "high" signal. Outputs the buffer 50 to disable.

At this time, the CPU has a jump table value of the first ROM 10 and calls the banking program to execute the corresponding jump table program.

At this time, when the program execution of the first ROM 11 is completed, the OFF signal of the first ROM 11 is applied to shift the latch F ₁ to the “high” signal, so that the first ROM 11 is turned off and the NAND gate ( Since G ₄ ) is output as a "low" signal, the program is executed again in the RAM 30.

As described above, the program is divided into several ROMs and the necessary programs are stored in RAM, and the rest of the programs can be directly accessed from the ROM to proceed with a large program with a small amount of memory. It has the advantage of being useful not only for computers and peripherals but also for all devices that use memory.

Claims (1)

In a memory device using a banking program, a ROM 10 storing a banking program and a module program, a ROM selection control unit 2, a RAM 30 for transferring the corresponding program to the ROM 10, and the RAM ( RAM output control unit 40 for outputting the output control signal of 30) and buffer 50 for buffering the output of the RAM 40 and outputting by the predetermined output of the RAM output control unit 50 A memory device that divides a program into several parts and transfers some of them to RAM.

Images