KR940011038B1 - Operational function checking device and method thereof for microprocesses - Google Patents

Abstract

No content.

Description

Operation function checking device for microprocessor and its method

1 is a simplified block diagram illustrating an embodiment of the invention.

2 is a simplified block diagram illustrating an embodiment of a parallel CRC used in the present invention.

* Explanation of symbols for main parts of the drawings

10 microprocessor 12 control circuit

20: parallel CRC 22: parallel CRC generator

24: expected result generating register 26: comparator

28: comparison timing circuit 30: single watchdog timer

40: accurate time monitoring timer 50: parity checker

60 parity ROM 70 error logic circuit

The present invention is directed to an apparatus and method for providing a single microprocessor basic control architecture that provides an inherent self-diagnostic capability that is sufficiently rigid that the structure is free of significant failures.

Recently, microprocessors have begun to be used in almost all areas of electronics facility design. This trend is developed because the microprocessor is free to use, cheap, easy to handle and powerful. There is a wide range of electronics available for microprocessors. The area includes command and control applications that require extreme reliability or the ability to detect and suppress improper operation of the system or critical portions of the system. A common difficulty stems from the microprocessor's self-contained nature, which makes self-diagnosis very difficult to determine if the processor and associated support devices (RAM, ROM, etc.) are operating properly.

The conventional solution to this problem is to design two completely separate microprocessor systems running the same program simultaneously and to demonstrate proper operation through a comparison technique on the selected outputs of the two systems. The method has the obvious drawback of adding the cost and complexity of the comparison circuit to the cost of doubling all the functions of the system, including the microprocessor, RAM, ROM and input / output functions. Another difficulty for dual processors is the problem of synchronization of the two microprocessors. The microprocessor must be synchronized so that the comparison output of the two systems occurs at the exact same time. If these outputs do not occur at the same time, the comparison logic will display an error. Therefore, circuitry must be provided to ensure synchronization of the microprocessor. Appropriate precautions should also be selected to provide immunity to power line transients.

The present invention relates to an apparatus and method for monitoring and verifying the correct operation of a microprocessor system. The present invention uses four circuits to perform the checking function. These circuits include a parallel cyclic redundancy checker (CRC) to monitor the microprocessor's address and data lines, a single watchdog timer to verify proper response in power-up sequence, and an appropriate microprocessor runtime watchdog timer. Accurate runtime watchdog timer and program ROM to verify is a parity ROM to be used with the program ROM to verify that it provides valid data to the microprocessor.

It is an object of the present invention to provide a new and improved apparatus and method for checking the operating functions of microprocessors and associated systems.

It is a further object of the present invention to provide a single microprocessor basic control architecture that provides an inherent self-diagnostic capability that is sufficiently rigid that the structure is practically fault free.

It is another object of the present invention to provide an apparatus and method for checking microprocessors and microprocessor systems without duplicating the actual part of the electronics associated with the processor.

Hereinafter, the present specification will be described in more detail with reference to the accompanying drawings.

Referring to the drawings, FIG. 1 is a simplified block diagram of an operation function checking apparatus for checking the correct initial setup, correct execution sequence, correct execution timing and correct instruction execution function of a microprocessor implementing the present invention at power-up. 1 depicts a control circuit 12 that is shown separately from the microprocessor 10 but may be an actual part of the microprocessor 10. This is because the microprocessor 10 can provide the necessary control impulses. The control circuit 12 may be a simple latch that the microprocessor can write to and use one or more bits to provide instructions that will also be discussed in the specification. The control circuit 12 has an input coupled to the address bus 16, the data bus 17 and the clock 18 of the microprocessor 10 and has a start output 13, a reset output 14 and a stop output ( 15).

A parallel cyclic redundancy checker (CRC) 20 having an error output 21 coupled to an error logic circuit 70 is coupled to the address bus 16, data bus 17 and clock 18 of the microprocessor 10. do. The parallel CRC 20 has a stop input that is also coupled to the stop output 13 of the control circuit 12.

A single watchdog timer 30 having an error output 32 coupled to the error logic circuit 70 is at the input of the timer a clock 18 of the microprocessor 10 and a reset output 14 of the control circuit 12. Is coupled to.

An accurate time monitoring timer 40 with an error output 42 coupled to the error logic circuit 70 and an execution output 44 coupled to the stop input of the parallel CRC 20 is coupled to the clock of the microprocessor 10. And a stop input coupled to the start output 13 and a stop input coupled to the stop output 15 of the control circuit 12.

The parity checker circuit 49 in this particular embodiment, which consists of a parity checker 50 having an error output 52 coupled to the error logic circuit 70, comprises a clock bus and a data bus 17 of the microprocessor 10. 18). Parity ROM 60 has parity output 62 coupled to parity input of parity checker 50 and address input coupled to address bus 16 of microprocessor 10.

The clock 18 of the microprocessor 10 may also be called a control line, which appears in every processor and sets the frame of reference and identifies the information provided by the processor. Timers 30 and 40 are used for the clock to calculate the clock transition point during each instruction cycle.

The error logic circuit 70 is a circuit that will operate when an error is detected in the processor 10, and thus, in a simple example, the error logic circuit 70 may appear as a device that performs a logical OR function. The error logic circuit 70 may indicate an error or may be set to disable the entire system (not shown) or switch to a second system (not shown) when an error is detected. Therefore, the error logic circuit 70 may vary in response depending on the application of the processor.

Parallel CRC 20 is used to calculate CRCs on data and address buses 17 and 16, respectively, while microprocessor 10 executes the programs of the CRCs. Parallel CRC 20 runs for a given number of processor cycles and the result of the CRC is compared to a known value stored in memory by a program or in ROM during the manufacture of the present invention.

CRC checking, the generation of a stop signal, and the comparison between the correct CRC and the actual CRC are all done in the hardware outside of the microprocessor 10 because it does not know that the microprocessor 10 is operating correctly. If improperly operated, microprocessor 10 cannot be trusted to produce accurate results.

Parallel CRC 20 generates symbol analysis consisting of all states of the address line and all states of the data line. The symbol is compared to the symbol previously selected to verify that the address line and the data line contain the appropriate information and that the information appears in the proper sequence. The check verifies that the microprocessor 10 executes the program instructions in the proper sequence.

By executing the instructions of each microprocessor and writing the result of the instructions to the address of the memory space, the parallel CRC 20 will verify that all instructions that the microprocessor can perform are executed correctly. For example, if a program is written such that all arithmetic operations that the microprocessor can perform are used for some data as input and the output is written to memory space, parallel CRC 20 will monitor the recording of the results in memory. If the result is wrong, the CRC will be wrong. Another example is the task of jumping instructions. The program is written so that jumps are made through the ROM memory space, and if a particular jump is done incorrectly, the CRC result will be wrong and the CRC test will fail.

Thus, parallel CRC 20 is used to verify that within a given piece of code the instruction is properly read from ROM or RAM, the program flow is properly processed, and the information written to the memory is correct.

2 is a simplified block diagram of a parallel CRC 20. 2 shows an embodiment of a parallel CRC 20 that constitutes a parallel CRC generator 22 coupled to a data bus 17, an address bus 16 and a clock 18. The CRC 20 additionally includes a comparator 26 having a predetermined result generating register 24 and a parallel CRC generator 22 and an input coupled to the predetermined result generating register 24. CRC 20 also includes a comparison timing circuit 28 having an output coupled to the input of comparator 26 and an input coupled to start output 13 and stop output 44. The predetermined result register 24 is used to store the predetermined result of the CRC generation. The predetermined result register 24 is loaded by the microprocessor 10 before CRC generation begins. The comparator 26 is used to compare the result stored in the predetermined result issue register 24 after the CRC check is completed. If the actual result is different from the value stored in the expected result register 24, the comparator 26 generates an error.

While parallel CRC 20 is used, data bus 17 and address bus 16 must be scheduled. Execution of the program should result in the same address and data bus activity each time the test runs. This is necessary because the CRC test requires consistent data to perform CRC at each same time. This means that every time the program is run, the program correctly selects the same branch, and every time the program is run, the result of each calculation is exactly the same, and any memory that is read each time the program is run has exactly the same data. It means to include. If the microprocessor 10 does not perform certain tasks, these suppressions prevent the parallel CRC 20 from being used to constantly monitor the microprocessor 20. In recent applications, the CRC test is performed periodically as a "health check" of the microprocessor 10 instead of being performed as a regular test. The particular application of the microprocessor 10 will dictate the frequency at which the test should be performed. Referring to FIG. 1, the control circuit 12 sends a start signal through the start output 13. Upon completion of a given program, parallel crc 20 is stopped by timer 40 via stop output 44. When the CRC 20 receives the stop signal 44, the CRC 20 compares the result with the intended result. If the two results do not match, an error signal is understood and generated in the CRC 20 and sent to the error logic circuit 70. It will be appreciated by those skilled in the art that the parallel CRC generator 22 can generate a CRC value along every line of the data bus 17 and address bus 16 in each clock period of the clock 18. There will be. This is a faster clock than clock 18 because it performs n steps in parallel for each clock cycle of clock 18, where n is the sum of the number of lines of data bus 17 and address bus 16. It can be done without requiring.

The CRC test reads each location of the device during the CRC check and can therefore be used to verify the contents of the ROM, RAM or other storage (not shown) used by the microprocessor 10. Reading each location of a device is to match the contents of the device to the data bus according to the address of the data. Parallel CRC 20 will then perform a CRC check on each of these pieces of data and issue a composite CRC value. The value can be stored as a symbol of a specific part of the memory.

The second part of the microprocessor verification is made by the single watchdog timer 30. The circuit is a timer that turns off the system clock 18. The watchdog timer 30 is started by hardware when a reset signal is detected at the microprocessor. Once the single watchdog timer is activated, the microprocessor must restart watchdog timer 30 before timer 30 reaches its final value. If the timer is not reset by the control circuit 10, the timer will time out and an error signal will be generated to the error logic circuit 70.

The single watchdog timer 30 is used to verify that the microprocessor 10 executes exactly at the point where it can accurately respond to the power-on reset signal and at least reset the timer. The single watchdog timer 30 also performs a watch function among various special application functions performed by the microprocessor 10. Since the microprocessor 10 must restart the timer 30 periodically, if the microprocessor 10 misses restarting the timer, the timer 30 will generate an error signal. In general, the missed restart is an indication that the processor is not operating correctly.

The third part of the processor verification is the correct timekeeping timer 40. Watchdog timer 40 is used to verify that the microprocessor performs operations in the correct sequence and amount of time that the microprocessor normally selects to perform the function. The correct timekeeping timer 40 turns off the clock 18 of the microprocessor 10 and thus increments the timer 40 each time the microprocessor 10 executes another instruction. When the timer 40 times out, the presence of one instruction cycle in length outputs a pulse on the execution output 44. The microprocessor 10 must match because it writes the pulse to the I / O port at the exact time the timer times out. In this preferred embodiment, the control circuit 12 acts as an I / O port and outputs a stop command on the stop output 15 to the correct time monitoring timer 40. If the pulse from the control circuit 12 does not occur at the exact same time as the " execute " pulse from the timer 40, the program does not execute the correct sequence or the microprocessor 10 does not execute the instruction at the correct amount of time. It will be an error to tell you not to. In both cases, the processor does not operate correctly and the signal goes from the error output 42 to the error logic circuit 70.

The fourth part of the processor verification is the parity check on the program ROM of the microprocessor using the parity checker circuit 49. The parity check is made by adding a 1-bit parity ROM 60 which extends the width of the program ROM by 1 bit. The table of contents of the parity ROM is then set to perform parity for each instruction on the program ROM odd parity. If the command read according to 1-bit parity indicates good parity, the hardware will generate an error message to the error logic circuit 70 via the error output 52.

The present invention allows microprocessors to be used in situations where there is a lack of capability to demonstrate proper operation. In addition, the cost is greatly reduced because no parallel synthetic microprocessor architecture is required.

Claims (3)

An operating function checking apparatus for a microprocessor, comprising: a parallel CRC having a microprocessor, an error logic circuit, first and second inputs and an output of a parallel CRC coupled to the error logic circuit, and the first of the parallel CRC. An address bus of the microprocessor coupled to an input, a data bus of the microprocessor coupled to the second input of the parallel CRC checker, an input coupled to the microprocessor, and an output coupled to the error logic circuit. A parity checker circuit having a single watchdog timer, an accurate time watchdog timer having an input coupled to the microprocessor and an output coupled to the error logic circuit, and an input coupled to the microprocessor and an output coupled to the error logic circuit. Microprocessor for comprising a Motion function checking device. An operating function checking apparatus for a microprocessor, comprising: an error logic circuit, a control circuit coupled to the microprocessor having first, second and third outputs, and a first coupled to one of the data bus and the address bus, respectively. A parallel CRC having a first and a second input, a third input coupled to the first output of the control circuit, a fourth input coupled to the error logic circuit and an output, a first input coupled to the microprocessor, the A single watchdog timer having a second input coupled to the second output of the control circuit and an output coupled to the logic circuit, a first input adapted to receive a clock input from the microprocessor, the first output of the control circuit A second input coupled to the third input, a third input coupled to the third output of the control circuit, a first output coupled to the fourth input of the parallel CRC, and the error logic circuit. Accurate timekeeping timer with a second output coupled, a first input coupled to the data from the microprocessor, a parity checker with a second input and output coupled to the error logic means, and the address bus of the microprocessor And a parity memory having an input coupled to and an output coupled to the second input of the parity checker. An operating function checking method for a microprocessor, comprising: providing a microprocessor, accumulating cycle redundancy checks for data and addresses from the processor over a given number of processor cycles, and repeating the CRC repeated from the repetition step. Comparing with the stored data, signaling an error if the repeated CRC and the stored data do not match, starting a single watchdog timer, and from the microprocessor before the counter reaches zero. Delivering a reset signal to the single watchdog timer; signaling an error if the reset signal is not delivered before the counter reaches zero; starting an accurate timekeeper timer at the start of processor operation; Count each instruction cycle in the processor Sending a stop signal from the microprocessor to the correct timekeeping timer at substantially the same time that the correct timekeeping timer stops, and stopping the correct timekeeping timer at a predetermined count; Signaling an error if the signal and the stop of the count do not coincide, adding a parity bit to a memory containing a program executed by a microprocessor, and parity for each instruction contained in the program ROM Programming a table of contents of the parity ROM to have a predetermined parity, and signaling an error if a parity that does not match the predetermined parity is detected.

Images