KR940010514A - Frame Memory Malfunction Detection System - Google Patents

Frame Memory Malfunction Detection System Download PDF

Info

Publication number
KR940010514A
KR940010514A KR1019920018275A KR920018275A KR940010514A KR 940010514 A KR940010514 A KR 940010514A KR 1019920018275 A KR1019920018275 A KR 1019920018275A KR 920018275 A KR920018275 A KR 920018275A KR 940010514 A KR940010514 A KR 940010514A
Authority
KR
South Korea
Prior art keywords
signal
frame
data
generating
malfunction detection
Prior art date
Application number
KR1019920018275A
Other languages
Korean (ko)
Other versions
KR100205471B1 (en
Inventor
김세중
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019920018275A priority Critical patent/KR100205471B1/en
Publication of KR940010514A publication Critical patent/KR940010514A/en
Application granted granted Critical
Publication of KR100205471B1 publication Critical patent/KR100205471B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking

Landscapes

  • Synchronizing For Television (AREA)
  • Television Systems (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

본 발명은 프레임메모리 오동작 검출시스템에 관한 것으로서, 영상신호의 수직귀선구간에 프레임 동작판별신호를 삽입한 다음 현재 신호와 한 프레임이전의 신호에 삽입된 판별신호를 검출하여 프레임 메모리의 오동작 유무를 자기진단 하도록 하는 것이다.The present invention relates to a frame memory malfunction detection system, which inserts a frame operation discrimination signal into a vertical retrace section of an image signal, detects a discrimination signal inserted into a current signal and a signal before one frame, and detects whether there is a malfunction of the frame memory. To make a diagnosis.

이와같은 본 발명은 복합영상신에서 필드신호를 검출하여 발생하는 필드신호발생수단과, 상기 복합영상신호에서 수평동기를 검출하는 수평동기검출수단과, 상기 필드신호발생수단과 수평동기발생수단의 출력신호에 의해 프레임신호를 생성하고 그 프레임신호의 수직귀선구간에 프레임판별신호를 삽입하는 프레임동작판별신호 삽입 수단과, 상기 프레임동작판별신호 삽입수단의 현재신호와 한 프레임 이전의 신호에 삽입된 판별신호을 검출하는 프레임동작판별신호 검출수단으로 구성으로써 달성되는 것이다.As described above, the present invention provides a field signal generating means for detecting a field signal in a composite video scene, a horizontal synchronous detecting means for detecting horizontal synchronous in the composite video signal, and outputs the field signal generating means and a horizontal synchronous generating means. A frame motion discrimination signal inserting means for generating a frame signal by means of a signal and inserting a frame discrimination signal into a vertical retrace section of the frame signal, and discrimination inserted into the current signal of the frame motion discrimination signal inserting means and a signal one frame before This is achieved by configuring the frame operation discrimination signal detecting means for detecting the signal.

Description

프레임 메모리 오동작 검출시스템Frame Memory Malfunction Detection System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명 프레임메모리 오동작 검출시스템 구성도,1 is a block diagram of a frame memory malfunction detection system according to the present invention;

제2도는 제1도 프레임 판별신호 삽입부에 대한 상세구성도,2 is a detailed configuration diagram of the first frame discrimination signal inserting unit;

제3도는 제2도의 프레임동작 판별신호 검출부에 대한 상세 구성도.FIG. 3 is a detailed configuration diagram of the frame operation determination signal detection unit of FIG.

Claims (4)

입력 복합영상신호를 디지탈신호로 변환하는 아날로그/디지탈 변환수단과, 상기 복합영상신에서 필드신호를 검출하여 발생하는 필드신호발생수단과, 상기 복합영상신호에서 수평동기를 검출하는 수평동기검출수단과, 상기 필드신호발생수단에서 얻어진 필드신호를 수평동기발생수단의 수평동기신호에 동기시켜 프레임신호를 생성하고 그 프레임신호의 수직귀선구간에 프레임판별신호를 삽입하여 디지탈 복합영상신호와 합성하는 프레임동작판별신호 삽입수단과, 상기 프레임동작판별신호 삽입수단을 통한 프레임을 저장하는 프레임메모리수단과, 상기 프레임동작판별신호 삽입수단의 현재신호와 프레임메모리수단의 한 프레임 이전의 신호에 삽입된 판별신호를 수평동기 및 필드 신호발생수단에 의해 검출하는 프레임동작판별신호 검출수단으로 구성함을 특징으로 한 프레임메모리 오동작 검출시스템.Analog / digital conversion means for converting an input composite video signal into a digital signal, field signal generation means for detecting a field signal in the composite video scene, horizontal synchronous detection means for detecting horizontal synchronization in the composite video signal, and And a frame operation for generating a frame signal by synchronizing the field signal obtained by the field signal generating means with the horizontal synchronizing signal of the horizontal synchronizing means, and inserting a frame discrimination signal into the vertical retrace section of the frame signal to synthesize the digital composite video signal. A discrimination signal insertion means, a frame memory means for storing a frame through the frame motion discrimination signal inserting means, a discrimination signal inserted into a current signal of the frame motion discrimination signal inserting means and a signal one frame before the frame memory means; Frame motion discrimination signal detecting means detected by horizontal synchronizing and field signal generating means. Frame memory malfunction detection system, characterized in that the configuration. 제1항에 있어서, 프레임동작판별신호 삽입수단은 필드신호발생수단으로부터 발생된 필드신호를 클럭신호로 하여 분주시키는 플립플롭(103a)와, 상기 플립플롭(103a)의 출력 펄스를 2비트로 카운트하는 카운터부(103d)와, 상기 수평동기발생수단의 수평동기신호와 필드신호발생수단의 필드신호를 조합하여 제어신호를 발새 는 제어신호발생부(103b)와, 상기 제어 신호발생부(103b)로 부터 출력된 제어 신호에 동기시켜 카운터부(103d)의 병렬데이타를 직렬데이타로 변환하는 병렬/직렬 변환부(103e)와, 상기 수평동기 신호와 아나로그/디지탈변환수단의 출력신호를 조합하여 선택신호를 발생하는 선택신호발생부(103c)와, 상기 선택신호발생부(103c)의 선택신호에 따라 아날로그/디지탈변환수단으로 부터 출력된 디지탈신호와 병렬/직렬 변환부의 직렬데이타를 선택하여 프레임메모리수단에 출력하는 신호선택부(103f)로 구성함을 특징으로 한 프레임메모리 오동작 검출시스템.2. The apparatus according to claim 1, wherein the frame motion discrimination signal inserting means includes a flip-flop 103a for dividing the field signal generated from the field signal generating means as a clock signal and counting the output pulse of the flip-flop 103a with 2 bits. A control signal generator 103b for generating a control signal by combining a counter 103d, a horizontal synchronous signal of the horizontal synchronous generating means and a field signal of a field signal generating means, and the control signal generator 103b. Selects by combining the parallel / serial conversion section 103e for converting the parallel data of the counter section 103d to serial data in synchronization with the control signal outputted from the control signal and the output signal of the horizontal synchronization signal and the analog / digital conversion means. Selection signal generator 103c for generating a signal and digital data output from the analog / digital conversion means and serial data of the parallel / serial converter according to the selection signal of the selection signal generator 103c are selected. And a frame memory malfunction detection system characterized in that it consists of a signal selecting section (103f) to output to the frame memory means. 제1항에 있어서, 프레임동작판별신호 검출수단은 상기 필드신호발생수단의 필드신호와 수평동기신호를 조합하여 제어신호를 발생하는 클럭 신호발생부(105a)와, 상기 클럭신호발생부(105a)의 클럭 신호에 동기시켜 프레임메모리수단의 출력 데이타를 출력하는 플립플롭(105b)과, 상기 플립 플롭(105b)의 직렬데이타를 병렬데이타로 변환하여 출력하는 직/병렬 변환부(105c)와, 상기 직렬/병렬 변환부의 병렬데이타 및 프레임동작판별신호 삽입수단의 데이타를 버퍼링하는 버퍼부(105d)와, 상기 버퍼부(105d)의 출력 데이타를 감산하는 감산기(105e)와, 상기 감산기(105e)외 출력신호를 논리화하여 오동작검출신호를 출력함과 아울러 표시하는 오동작검출표시부(105f)로 구성함을 특징으로 한 프레임메모리 오동작 검출시스템.2. The apparatus according to claim 1, wherein the frame motion discrimination signal detecting means comprises a clock signal generating portion (105a) for generating a control signal by combining the field signal and the horizontal synchronizing signal of the field signal generating means, and the clock signal generating portion (105a). A flip-flop 105b for outputting the output data of the frame memory means in synchronization with a clock signal of the same, a serial / parallel converter 105c for converting the serial data of the flip-flop 105b into parallel data and outputting the parallel data; A buffer unit 105d for buffering the parallel data of the serial / parallel conversion unit and the data of the frame operation discrimination signal inserting means, a subtractor 105e for subtracting the output data of the buffer unit 105d, and the subtractor 105e. And a malfunction detection display portion (105f) for outputting and displaying a malfunction detection signal by logicalizing an output signal. 제3항에 있어서, 오동작검출표시부(105f)는 상기 감산기(105e)로부터 감산된 데이타의 최상의 비트를 반전시키는 인버터게이트(I1)와, 상기 인버터게이트(I1)를 통해 반전된 최상의 비트와 감산기(105e)로 부터 감산된 데이타의 이하의 비트를 낸드화시켜 오동작검출신호를 출력하는 낸드게이트(NAND1)와, 상기 낸드게이트(NAND1)의 오동작검출신호를 반전하여 출력하는 인버터게이트(I2)와, 상기 낸드게이트(NAND1)의 오동작검출신호에 따라 스위칭되어 오동작을 표시하는 발광소자(LD1)로 구성함을 특징으로 한 프레임메모리 오동작 검출시스템.The malfunction detection display unit 105f of claim 3 further includes an inverter gate I1 for inverting the most significant bit of the data subtracted from the subtractor 105e, and the best bit and subtractor inverted through the inverter gate I1. A NAND gate NAND1 outputting a malfunction detection signal by NANDizing the following bits of data subtracted from 105e), an inverter gate I2 inverting the malfunction detection signal of the NAND gate NAND1, and outputting the malfunction detection signal; And a light emitting element (LD1) which is switched in accordance with a malfunction detection signal of the NAND gate to indicate a malfunction. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920018275A 1992-10-06 1992-10-06 Error detecting system for frame memory KR100205471B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920018275A KR100205471B1 (en) 1992-10-06 1992-10-06 Error detecting system for frame memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920018275A KR100205471B1 (en) 1992-10-06 1992-10-06 Error detecting system for frame memory

Publications (2)

Publication Number Publication Date
KR940010514A true KR940010514A (en) 1994-05-26
KR100205471B1 KR100205471B1 (en) 1999-07-01

Family

ID=19340654

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920018275A KR100205471B1 (en) 1992-10-06 1992-10-06 Error detecting system for frame memory

Country Status (1)

Country Link
KR (1) KR100205471B1 (en)

Also Published As

Publication number Publication date
KR100205471B1 (en) 1999-07-01

Similar Documents

Publication Publication Date Title
FI925436A (en) VIDBILDSTELEVISION
KR930014148A (en) Motion detector
KR890015609A (en) TV device
KR960011945A (en) Digital processing equipment
KR880014478A (en) Computer video demultiplexer
KR970705240A (en) LETTER-BOX TRANSFORMATION DEVICE
KR950026175A (en) Encoder Flicker Reduction Device
KR970004804A (en) Subtitle Data Position Control Circuit of Wide Vision
US20040183945A1 (en) Image processor with frame-rate conversion
KR940010514A (en) Frame Memory Malfunction Detection System
KR100241443B1 (en) Interlace mode and non-interlace mode conversion circuit
KR100259139B1 (en) Input buffer controlling apparatus for audio decorder
KR0140918B1 (en) Overhead timing detection circuit of the synchronous transport apparatus
KR950030589A (en) An apparatus and method for converting interlaced scan image to interlaced scan image
KR950009661B1 (en) Scanning speed converting circuit of picture system
KR960012495B1 (en) Macro block address memory for hdtv
KR970003427B1 (en) Converting device of scan speed of digital video signal
KR960028384A (en) Anti-CC / ARM Inverter Using CCI 601 Video Signal
KR910007371A (en) Video I / O Device of Static Image Telephone for General Exchange Line
KR900019493A (en) Color image display device of color LED
KR890017954A (en) Subscreen Enlargement and Reduction Circuitry and Method for Television or Video Tape Recorders
SU1188727A1 (en) Synchronizing unit for device to display information
SU1469518A1 (en) Device for representing an image on screen of tv receiver
JP3813841B2 (en) Video signal input device and image display device having the same
JPH0497661A (en) Frame synchronizing device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070329

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee