KR940010225B1 - Graphic display processing system with control method - Google Patents

Abstract

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Description

Figure processing device and its operation method

1 is a block diagram showing an overview of the present invention.

2 is a block diagram of a graphics processing apparatus according to the present invention.

3 is a diagram showing an example in the case of displaying one pixel in four bits.

FIG. 4 is a diagram showing an example of a specific configuration of a logic address calculation unit in FIG.

FIG. 5 is a diagram showing a specific configuration example of the physical address computation unit in FIG. 2; FIG.

FIG. 6 is a diagram showing an example of the specific configuration of the color data calculating section in FIG.

7 is a functional explanatory diagram of each field of a micro instruction.

Fig. 8 is a diagram showing the bit structure of the display memory in each mode.

9 is an explanatory diagram of a pixel address corresponding to FIG. 8;

10 is an explanatory diagram of a spatial arrangement of the display memory in the 4-bit / pixel mode.

11 is a diagram schematically showing the flow of drawing operations of one pixel (4 bits / pixel).

FIG. 12 is a diagram illustrating components in the case of converting to a physical address corresponding to a logical address in FIGS. 4 and 5 and adding some additional functions.

13 is an explanatory diagram of the relationship between physical addresses, logical address spaces, and display screens in a mode (4 bits / pixel).

14A to 14C are explanatory diagrams related to FIG.

FIG. 15 is a diagram showing correspondence between a bit mode and a bit address indicating a pixel position in one word corresponding thereto. FIG.

16A to 16D are explanatory diagrams of the relationship between mask data and bit addresses.

FIG. 17A is a diagram showing a basic arithmetic processing in address conversion; b is a diagram showing a bit address offset value;

18 is a diagram showing an example of linear drawing in the case of using the present invention.

FIG. 19 is a diagram showing an example of application of the transfer of pixel information, for convenience, omission of having nothing to do with transfer processing in FIGS. 4 to 6;

20A, 19B and 19D are explanatory diagrams of the operation.

21 is a diagram showing an example of transmission of one pixel data.

Fig. 22 is a diagram schematically showing the flow of the transfer process.

Fig. 23 is a diagram showing a pointer movement direction of transmission in the quadrangular area designation.

24 is a configuration of arithmetic control of a pixel position, showing only those related to FIGS. 4 to 6;

25A to 25E show a format of a transmission (copy) command.

26 is a conceptual diagram of its operation.

27A is a diagram showing an example of the structure of a code register, b, c is a diagram showing an example of the format of a pattern command.

Fig. 28 is a flowchart of processing of a kopi command.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a raster scanning type CRT (cathod ray tube) display device and the like, which includes a microprocessor for inputting / outputting data, collecting data, and displaying graphics. A graphic processing apparatus having a drawing function for controlling by a microprogram and a method of operating the same.

Most of the conventional CRT controllers are dedicated to display control and do not have a drawing function. For example, US Pat. No. 4,149,264. In addition, even if there is an image processing apparatus in which the graphic processing function is realized with an integrated circuit, it is only processing the graphic display data of a single color displaying one pixel with one bit. However, with the advancement of information processing, many cases of multicolor or multi-gradation image processing are performed, and the processing speed at that time becomes a problem. For example, in the case of multicolor (n-color) or multi-gradation (n-gradation) processing, when rewriting the stored contents, the same image processing is repeated n times or n times in order to display one pixel of one bit. Image processing was necessary.

Therefore, there is a problem that the processing time of n times is required for the binary image processing. Although a method of processing with one processing unit for each of the n display memories is considered, there has been a problem that the apparatus becomes larger and more complicated and the load on the central processing unit increases. Consider a case where the drawing process is executed by drawing a straight line in the XY coordinate space with any one point as the origin. Assume the case of connecting two arbitrary points P _S (X _S, Y _S ) and P _E (X _E , Y _E ) in a straight line. In this case, the inclination of the straight line is calculated from the coordinate values of these two points, and the coordinate values of the points on the straight line are calculated to create figure data for each point, and then write. Although this process is performed in sequence for all the points existing on the straight line, the calculated coordinate values are completely independent of the memory address of the display memory into which the figure data is written. It needs to be converted to a memory address. However, since one word of the display memory contains single or plural pixel data, the calculated logical address is divided into two physical addresses in the form of a memory address of the display memory or a bit address indicating the pixel position. Will be converted.

To convert from a logical address to a physical address, it is necessary to know the physical address corresponding to the origin and the size of the horizontal direction of the screen memory. That is, since the logical address is information indicating the relative position from the origin, when the logical address is (X, Y), the horizontal direction of the screen memory is multiplied by Y in the vertical direction (Y direction), and the horizontal direction (X Direction), the target memory address can be calculated by adding or subtracting the value of X to the physical address corresponding to the origin. Further, the target memory address can be calculated by adding and subtracting the value obtained by dividing the value of X by the number of pixels included in one word to the physical address corresponding to the origin. Further, by setting the remainder obtained by dividing the value of X by the number of pixels included in one word as a bit address, a physical address for processing figure data is obtained.

However, until now, the calculation of the logical address and the conversion to the physical address have been entirely performed by software programs. When using a general-purpose microprocessor, one pixel data is stored in the display memory. It is a fact that the process was not able to be speeded up by several hours from several microseconds to several tens of microseconds.

In the figure processing apparatus for creating figure display data, the figure display data transfer processing is performed in the display memory, but the processing speed has been a problem.

For example, there is a case where one pixel data is to be transferred to another pixel position. Usually, one word of the memory stores data of a plurality of pixels that are continuous in the horizontal direction. Therefore, when certain pixel data is transferred to another pixel position, a shift process or an extraction process of the source pixel data is required to make the bit positions of the operation uniform. Conventionally, this transfer process is performed by software. For example, in the case of the process of transferring data of a quadrangular area, a process such as moving a pointer for designating a source pixel and a destination pixel, counting the transfer frequency, and the like Is added. As a result, when a general-purpose microprocessor is used, several microseconds to several tens of microseconds are required for transfer processing per pixel, and therefore, the speed of the process has been a problem.

SUMMARY OF THE INVENTION The present invention provides a figure processing apparatus and a method of operating the same, which realize speeding-up processing such as rewriting, drawing, and transferring pixel data in multicolor and multi-gradation.

In addition, there are other well-known examples of this type of graphic processing device in addition to GB2087 696A.

An object of the present invention is to provide a graphic processing apparatus and a method of operating the same, which can be drawn at substantially the same processing speed as in the case of a binary image even in the case of multi-color or multi-gradation in which one pixel is represented by a plurality of bits.

Another object of the present invention is to provide a graphic processing apparatus and a method of operating the same, which can calculate a display memory at high speed from logical coordinate values of an image.

According to the present invention, there is provided a graphic processing apparatus for accessing a display memory (13) in which one pixel data is composed of a plurality of bits, and the plurality of pixel data are used as an access unit, comprising: a memory address of a word of the display memory; The physical address calculation unit 320 for calculating the position information of the drawing point including the pixel address defining the pixel position within one word designated by this memory address, and the pixel data designated by the pixel address is updated in accordance with the drawing command. It provides a figure processing apparatus having a color data calculation unit 330 to.

Further, according to the present invention, a step of outputting an image of graphic pattern data and at least one pixel which is an image element of a unique point in a two-dimensional space of graphic pattern data in an address supplied to an output of an image of graphic pattern data is performed. And a step of specifying the number of bits of data in at least one pixel stored in the address, and the step of writing at least one pixel of data in the word with the number of bits in the specified number of at least one pixel. A method of operating a graphics processing device is provided.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram showing the overall configuration of a graphics processing apparatus according to the present invention, and a block diagram showing an example of a device to which the graphics processing apparatus according to the present invention is applied.

1, the figure processing apparatus includes an arithmetic unit 30 which writes, rewrites and reads and controls the display data in the display memory 13, and a controller which controls the arithmetic unit 30 in a certain order. It consists of 20. In addition, the display data read out from the display memory 13 by the graphics processing device is displayed on the display device 50 as a video signal by the display conversion device 40, and the display conversion device 40 and the display device. Reference numeral 50 constitutes information output means 40,50.

The arithmetic unit 30 controlled by the control unit 20 sequentially performs a pixel address consisting of an address of the display memory 13 and information specifying a pixel position in the display data of one word in the display memory 13. Calculates and reads one word of display data in the display memory 13 from the address information of the display memory 13 in the calculated pixel address. The display data read in this way is read in the pixel address. Has information for designating a plurality of bit positions corresponding to the designated pixel positions formed on the basis of the pixel position designation information, and only the bit of the predetermined pixel of the display data is written and a logic is calculated. It has a function of writing to the display memory 13 again.

Reference numeral 60 denotes an external calculator, in which the figure processing apparatus operates in accordance with the control data CDT of the command or parameter transmitted from the external calculator 60.

2 is a block diagram showing an embodiment of a figure processing apparatus according to the present invention.

In FIG. 2, the control device 20 includes a micro program memory 100, a micro program address register 110, a return address register 120, a memory command register 130, and a micro command decoder 200. ), A flag register 210, a pattern memory (RAM) 220, and a command control register 230.

In addition, the arithmetic unit 30 is composed of an arithmetic control unit 300 and a FIFO (First-In, First-Out) memory 400. The command control register 230 and the FIFO memory 400 constitute the command memories 230 and 400. The operation control device 300 is composed of a logical address calculation unit (A unit) 310, a physical address calculation unit (B unit) 320, and a color data calculation unit (C unit) 330.

In the A unit 310, the drawing point is mainly calculated according to the drawing algorithm, and in the B unit 320, the necessary address of the display memory is calculated, and the C unit 330 is written in the display memory. To calculate the color data.

FIG. 3 shows an example of the configuration of a display device that displays one pixel in four bits, and display data designated by the graphics processing device in FIG. 2 is displayed on the display device 50. As shown in FIG.

3, D ₀ , D ₄ , D ₈ , and D ₁₂ of the display data DT read out from the display memory 13 according to the address AD command from the figure processing apparatus (FIG. 2) are the display conversion apparatus. Supplied to a 4-bit parallel-to-serial converter 410 in 40. The video signal VD ₀ is obtained from this converter 410. Similarly, D _1, D ₅ , D ₉ , and D ₁₃ in the display data DT are supplied to the parallel-to-serial converter 420 in the display conversion device 40, and the video signal VD ₁ is obtained from this converter 420. . D _2, D ₆ , D ₁₀ , and D ₁₄ in the display data DT are supplied to the parallel-to-serial converter 430 in the display conversion device 40, and the video signal VD ₂ is obtained from this converter 430. Further, D _3, D ₇ , D ₁₁ , and D ₁₅ in the display data DT are supplied to the parallel-to-serial converter 440 in the display conversion device 40, and the video signal VD ₃ is obtained from this converter 440. . The video signals VD _{0 to} VD ₃ are sent to the video interface circuit 450 and displayed on the display device 50 after processing such as color conversion or DA conversion.

Next, a specific configuration example of each unit of the arithmetic and control device 300 will be described.

4 is a detailed view of the logical address operation unit 310, which is an A unit, and includes a FIFO buffer (FBUF) 3101 and a general register group (TROX, TROY, TR1X, TR1Y, TR2X, TR2Y, CPX, CPY) (3102). And area management registers (XNIM, YMIN) 3103 and (XMAX, YMAX) 3105, area judgment comparator (ACMP) 3104, endpoint registers (XEND, YEND) 3106, and end judgment comparator. (ECMP) 3107, source latches (SFTA, SLAV) 3108 and (SLAU) 3109, arithmetic logic operator (ALU) 3110, destination latch (DLA) 3111, bus A switch 3112, read buses (UBA, VBA) 3113 and 3114, and a write bus (WBA) 3115 are provided.

5 is a detailed view of the physical address computing unit 320, which is a B unit, and includes a destination latch (DLB and SFTB) 3201, an arithmetic operator (AU) 3202, and a source latch (SLBV) 3203. (SLBU) 3204, Offset Register (OFS) 3205, Screen Width Register (MW) 3206, Command Register (CR) 3207, General Purpose Registers (DPH, DPL, RWPH, RWPL, T2H, T2L) 3208, read bus (UBB) 3209, and write bus WBB (3210) are provided. The general-purpose register 3208 includes the current address registers DPH and DPL of the pixel unit command, the address registers RWPH and RWPL of the word unit command, and the working registers T2H and T2L.

6 is a detailed view of the color day calculation unit, which is a C unit. The C unit includes a barrel shift (BRLS) 3301, a color register (CL0, CL1, EC, EDG) 3302, a mask register (CMSK, GMSK) 3303, a color comparator (CLCMP) 3304, Logic operator (LU) 3305, write data buffer (WDBR) 3306, pattern RAM buffer (PBUF) 3307, pattern counter (PCNT) 3308, pattern control registers (PP, PS) , PE) 3309, read data buffer (RDBR) 3310, memory address registers (MARL, MARH) 3311, memory output bus 3312, memory input bus 3313, information output An input / output buffer circuit 3400 which is a means is provided. The mask register 3303 is composed of a register CMSK and a register GMSK.

Next, the operation of the configured embodiment as described above will be described. First, the basic operation of each element will be described.

The display control data CDT shown in FIG. 1, FIG. 2, etc., is a command or parameter sent from another apparatus such as a central processing unit, and is written to the memory (FIFO) 400 on one side and to the command control register 230 on the one side. Is written.

The command control register 230 stores various graphic bit modes, and according to this embodiment, one of five pixel modes can be selected as described later. This selection can be made by use data CDT.

The memory 400 is a so-called "Ferst-In, First-Out" (FIFO) memory, and instructions stored in the memory 400 are read by the operation control device 300, and the operation control device 300 It is stored in the FIFO buffer (FBUF) 3101 which is an internal register. In addition, some CIDs of this command information are transmitted to the address register 110.

The address register 110 manages an address of the microprogram memory 100, which is updated in synchronization with a clock. Micro-instructions are read from the microprogram 100 as shown in FIG. 7 in accordance with the address output from the address register 110. The command read out from the memory 100 is made up of 48 bits, as shown in FIG. 7, and a control mode such as # 0 to # 7 can be selected. The command is temporarily stored in the register 130, and the predetermined control signal CCS is generated through the decoder 200 operating in accordance with the selected mode of the command control register 230 to generate a predetermined control signal CCS. To control wealth. Here, the function of each field of the microinstruction in FIG. 7 will be described.

In FIG. 7, "RU" is an instruction to designate a register connected to the read bus (UBA) 3113. In FIG. "RV" is an instruction to designate a register connected to the read bus (VBA) 3114. "RW" is an instruction to designate a register into which data on the write bus (WBA) 3115 is written. "FUNCA" is an instruction to specify the operation of the arithmetic logic operator 3110 of the unit of A. "SET" is a command for designating a shift mode of the shifter SFTA added to the source latch 3108. "ADF-L" is an instruction for specifying the lower 4 bits of the next address returned to the microprogram address register 110. FIG. "AC" is an instruction to control the next address of the micro instruction. "ADF-H" is an instruction to designate the upper 6 bits of the next address returned to the microprogram address register 110. In each of the memory instructions # 4 to # 7, the upper six bits of the address cannot be updated. "FUNCB" is an instruction for specifying the operation mode of the calculation unit 3202 of the B unit. "ECD" is an instruction for specifying an execution condition of an operation. "BCD" is an instruction for specifying the condition of branching. "FLAG" is an instruction to designate reflection of the flag in the flag register 210. "V" is a command for specifying whether to test whether access to the display memory 13 is tested or not. "FIFO" is an instruction to control reading and writing to the FIFO 400. "LITERAL" is an instruction for specifying literal data of 8 bits. "LC" is a command for specifying a generation mode of literal data. "FF" is a command to control the set and reset of each special flip-flop. "S" is an instruction to specify the selection of the code flag.

"MC" is a command to control reading and writing of the display memory 13. "DR" is a command for controlling scanning of the pattern RAM. "BC" is a command for controlling the input path of the B unit to the arithmetic operator 3203. "RB" is an instruction to select the read and write registers of the B units.

The microinstruction has the above-described instructions, whereby the control device 20 controls the computing device 30.

The return address register 120 also stores the return address of the subroutine. The flag register 210 stores various condition flags. The pattern memory 220 stores basic patterns used for figure processing.

Next, the bit layout of each data used in the present embodiment will be described.

First, the graphic mode will be described.

In this embodiment, five different operation modes can be selected in accordance with the designation of the graphic bit mode GBM stored in the command command control register 230.

8A to 8E show the bit structure of one word of the display memory in each mode.

(a) 1 bit / pixel mode (GBM = 000)

This mode is used for displaying one pixel with one bit, such as a black and white image. One word of the display memory 13 stores 16 consecutive pixels of data.

(b) 1 bit / pixel mode (GBM = 001)

This represents one pixel with two bits. It can be used to display up to four colors or up to four gradations. Therefore, one word of the display memory 13 stores eight consecutive pixels of data.

(c) 4 bit / pixel mode (GBM = 010)

This represents one pixel with four bits. One word of the display memory 13 stores data of four consecutive pixels.

(d) 8 bit / pixel mode (GBM = 011)

This represents one pixel in eight bits. One word of the display memory 13 stores two consecutive pixels of data.

(e) 16 bit / pixel mode (GBM = 100)

This represents one pixel with 16 bits. One word of the display memory 13 corresponds to one pixel of continuous data.

8F illustrates an example of the command control register 230.

Next, the pixel address will be described.

9 illustrates the pixel address corresponding to each mode of FIG. 8. The register 3208 of the physical address computation unit manages a bit address WAD in which four bits are added below the memory address. The lower 4 bits of information WAD are used to specify the pixel position in one word, and operate in accordance with each bit / pixel mode. In the figure, a "*" mark indicates a bit unrelated to an operation.

Fig. 10 shows the spatial arrangement of the display memory 13 in the above section (c) using "4 bit / pixel mode" as an example. The memory address is assigned as a linear address as shown in the memory map of FIG. 10A, which is displayed as a two-dimensional image as shown in FIG. 10B. The horizontal axis of the screen is stored in the screen width register (MW) 3206 of FIG. 5, and this MW indicates how many bits the horizontal axis of the screen is configured. Therefore, in the 4-bit / pixel mode, the horizontal direction The pixel is displayed. In addition, since one pixel is displayed in four bits, data of one word is represented by data of four pixels continuous in the horizontal direction as shown in FIG. 10C. In the offset generating circuit 2001 in FIG. 5, " 4 " is generated as an offset value and stored in the offset register 3205. FIG. Therefore, it is understood that the offset value may be added or subtracted to move the physical address by one pixel in the horizontal direction. In order to move one pixel in the vertical direction, the value of the register (MW) 3206 may be added or subtracted. The above is the layout of the bits of data used in the present embodiment.

Next, an operation of storing image data in the display memory 13 by using the data will be described.

Control data CDTs such as commands and parameters sent from an external central processing unit are written to the FIFO memory 400 on one side and to the command control register 230 on the other side.

Here, an example in which the graphic bit mode (GBM) stored in the command control register 230 and designated is the 4 bit / 1 pixel mode (GBM = 010) will be described.

When the graphic bit mode GBM is designated as 4 bits / 1 pixel by the command control register 230, the data of one word in the display memory 13 thereafter is divided every 4 bits as shown in Fig. 8C. Are treated as.

Signals CDT such as commands and parameters from an external central processing unit are sequentially stored in the FIFO memory 400. The data stored in this memory 400 is taken into the FIFO buffer 3101 of the A unit 310. The data taken into the FIFO buffer 3101 are mutually transmitted and received between the internal bus 3113 and stored in respective necessary registers. It is input from the bus to the logic operator (ALU) 3110 via a source latch (SLAU) 3109 to perform a predetermined operation and the result is stored in a temporary destination latch (DLA) 3111. The result is then stored in the general register 3102 via a bus (WBA) 3115. The current coordinate point in the coordinate space of the parameter is stored in this general register 3102.

The current XY coordinates in the general register 3102 are read out via either of the read buses 3113 and 3114, so that the result of the calculation in the arithmetic logic operator (ALU) 3110 is destination latch (DLA). (3111) and stored in the general-purpose register group 3102 via the write bus 3115 again. These series of operations are executed in accordance with the instructions of the microprogram shown in FIG.

The data on the write bus 3115 are input to the area management registers 3103 and 3105, and are compared in the area determination comparator 3104. From the data, the comparator 3104 determines whether the minimum value of the X-axis or the maximum value of the X-axis, the minimum value of the Y-axis, or the maximum value of the Y-axis is transmitted, and the result of the determination is sent to the flag register 10.

The data of the write bus 3115 is stored in the end point register 3106 and input to the end decision comparator 3107 through this. The end judgment comparator 3107 compares the end points of the X-axis and the Y-axis stored in the comparator 3107 with the data in advance, and detects whether the end point and the data coincide. The comparison detection result is reflected in the flag register 210.

As described above, the results of the comparators 3104 and 3107 and the calculator 3110 are collected in the flag register 210 and input to the microinstruction decoder 200 to be used to convert the flow of the microprogram.

As described above, the A unit 310 operates to decode the X-Y coordinate values given by the parameters, and to interpret the commands such as drawing a line or drawing a circle, for example.

Next, the operation of the B unit 320 will be described with reference to FIG.

The display control data is input-initialized to the register 3208 via the bus (UBB), arithmetic operator (AU) 3202, destination latch (DLB) 3201, and bus (WBB) 3210. Data in the register 3208 is input to the operator (AU) 3202 through the read bus 3209 and the source latch 3204. The result calculated by this operator 3202 is temporarily stored in the destination latch 3201, and is output to the buses 3113, 3114, 3209, and 3210, respectively. Here, it is written to the register 3208 via the bus 3210. This register 3208 has two 16-bit one-word words in one word structure, and stores physical addresses in one 32-bit total word. This register 3208 has three types of 32-bit registers and can store three types of data. That is, the registers DP (DPL, DPH) of this register 3208 store the physical address of the actual drawing point corresponding to the current drawing point X-Y. Therefore, when the XY coordinate of the register 3102 of the A unit 310 moves, the physical address of the register DP moves correspondingly. The physical address can be changed by adding or subtracting a predetermined value (offset value up to the point to be moved) to the original physical address in the X-axis direction. You can add or subtract. That is, in accordance with the image mode designated by the offset generation circuit 2001, the offset register 3205 is set with a constant when the pixel address is moved by one pixel in the horizontal direction. By calculating this constant and data with the calculator 3202, a horizontal moving address is calculated. For example, when the pixel mode is " 1 bit / pixel mode, " the constant is 1, and shifting 1 pixel only shifts 1 bit. In the "4 bit / pixel mode", the constant becomes 4, and shifting by 1 pixel shifts 4 bits.

In addition, in order to move the pixel vertically here, the calculation by using the constant set in the screen width register 3206 enables the movement of one pixel.

As described above, the B unit 320 operates to obtain the actual physical address corresponding to the X-Y coordinates determined by the A unit 310.

Next, the operation of the C unit 330 will be described with reference to FIG.

The C unit 330 is connected to the display memory 13 shown in FIG. 10 by an output bus 3312 and an input bus 3313. The address information AD is first output to the output bus 3312 from the C unit 330, and then the data DT is output.

First, the address information AD is written to the memory address register 3311 via the read unit (UBB) 3209 via the B unit 320, and the (MARL) and (MARH) of the memory address register 3311. Is remembered. When the memory address stored in this register 3311 is sent to the display memory 13 via the output bus 3312, the designated 1 of this memory 13 is sent from the display memory 13 via the input bus 3313. The memory DT for displaying the word is read. The read display data DT is stored in the read data buffer 3310. Here, when the display data DT draws a figure, it is input into the calculator 3305.

Next, mask information (information for specifying which bit in one word is used as a mask) from the mask register 3303 is input to the calculator 3305. The mask information is also sent to the calculator 3305 from a register CMSK written directly from the write bus WBB 3210 or from a register GMSK storing data generated by the address decoder 2002 in one word. do.

Further, color information is selected by the color register 3302 and given to the calculator (LU) 3305. The calculator 3305 performs a logical operation according to the data DT, mask information, and color information, and outputs the result of the calculation to the write data buffer (WDBR) 3306. Further, the color information and the pattern information are designated by the address signals formed in the pattern counter (PCNT) 3308 and the drawing pattern registers (PP, PS, PE) 3309, so that the pattern RAM from the pattern memory (RAM) 220 can be used. It is stored in the buffer (PBUF) 3307.

In this way, the C unit 330 operates to change the color information.

Next, the method of drawing operation is demonstrated. 11 schematically shows the flow of drawing operations of one pixel in the case of 4 bit / pixel mode.

The data read out from the pattern memory 220 by the addresses specified in the drawing pattern registers (PP, PS, PE) 3309 and the pattern register (PCNT) 3308 is transferred through the pattern RAM buffer 3307 through the color registers 3302. CL0 and CL1 are stored. The data C _a , C _b , C _c , and C _d read out from the display memory 13 are stored in the read data buffer 3310. In this example, the color data, the read data, and the like are 4-bit color information or gradation information, respectively. One-bit pattern information is read out from the pattern memory 220, and color register 0 (CL0) or color register 1 (CL1) in accordance with " 0 " and " 1 " (X = 1 or X = 0) of the data. Is selected and supplied to the logical operator 3305. In the drawing of the lower 4 bits of the physical address information stored in the memory address register 3311, " 10 ** ", this information is mask information GMSK in the mask register 3303 through the address decoder 2002 in one word. Occurs. On the other hand, in the upper field except the lower 4 bits of the memory address register 3311, one word of the display memory 13 output as the display memory address is read. In the logical operator 3305, only the portion designated by the bit of "1" of the GMSK of the mask register 3303 is a type of logical operation, rewriting to the value of the color register, logical operations (AND, OR, NOR), and conditional drawing (reading). Drawing only when the color satisfies a predetermined condition). In the case where the bit / pixel mode is different, the generated GMSK information is different and the same operation is performed. In this manner, the data is again sent to the output bus 3312 from the address register 3311 and the register 3306 in the order of the address information AD and the data DT, and written to the predetermined address of the display memory 13.

As described above, according to the present embodiment, data for one pixel can be updated at one time by one read, update, and write process, so that the drawing with good processing efficiency can be achieved. Also, in a case other than the 16-bit / pixel mode, since the data of a plurality of pixels are arranged and processed in a 16-bit length, the use efficiency of the memory is good, and the data transfer efficiency between the other device and the display memory is also good. In addition, in this embodiment, since the operation modes for five types having different bit lengths per pixel are set, the configuration is highly versatile.

Next, the figure processing which can calculate the physical address corresponding to a logical address at high speed is demonstrated by this invention. That is, the case where address conversion is performed at high speed using the A unit 310 and the B unit 320 in FIG. 2 will be described.

FIG. 12 shows what is related to address conversion and in particular, which has been added in accordance with the configurations shown in FIG. 4 and FIG. The same code | symbol is used for the same thing as FIG. 4 and FIG.

The selector 3500 is controlled by the CCS and selects one of the data from the memory width register (MW) 3206 and the data from the offset data register (OFS) 3205 to operate the operator (AU) 3202. Supplies). The calculator 3202 calculates a physical address corresponding to the logical address.

Next, the physical address space, the logical address space corresponding thereto, and the display screen corresponding thereto will be described. FIG. 13 shows a physical address space in a mode in which one pixel is displayed in four bits, a logical address space corresponding thereto, or a display screen corresponding thereto. The relationship between the physical address as the size MW in the horizontal direction, the display memory in the logical address space, and the display screen is as shown. In the physical address space, four pixels are included in one word 16 bits (pixel data represented by four bits). In this case, one pixel is allocated to each memory plane for each color in the memory in the logical address space. This is synthesized so that one pixel displayed in 16 colors (or 16 gradations) is output on the screen. The data of four pixels in one word become pixel data continuous in the horizontal direction on the memory in the logical address space and on the display screen.

FIG. 14 shows the relationship between the physical address, the logical address, the memory width MW, and the pointer address PA shown in FIG. First, FIG. 14A shows the memory address MA and the bit address BA in the physical address space, and again shows the relationship between the display screen and the memory address MA. When the memory address of one word including pixels vertically adjacent to one pixel in one word specified in the memory address MA1 is MA2, the memory width MW is as shown in Fig. 14C. Any point (x, y) on the screen shown in Fig. 14A indicates that when the corresponding physical address is the memory address MA, and the bit address is indicated by BA, the pointer address is displayed as in Fig. 14B.

Incidentally, in the embodiment shown in FIG. 12, the setting mode for the bit mode register 230 has a function of efficiently processing even when data of one pixel is displayed in multiple bits (multicolor or multi-gradation). There are five different operation modes to choose from. This is by FIG. 8 above.

FIG. 15 shows the correspondence between the bit mode shown in FIG. 14 and the bit address indicating the pixel position in one word corresponding thereto. This bit address is made to coincide with the data start bit number of the pixel data. For example, in the 4 bit / pixel mode, [4] is stored as the bit address of the lower 4 bits of the pointer address register 3208 when the bits 4 to 7 of the pixel data are calculated by the pixel data operation unit 330. will be.

16A to 16D show the relationship between the mask data stored in the mask register 3303 and the bit address in the case of 4 bit / pixel mode. As described above, 4 is generated as a bit address when the bits 4 to 7 of the pixel data are calculated, but in this case, "1" is set in correspondence with only the bit where the pixel data operation is performed, and the pixel data "0" is set corresponding to the bits that do not require operation. That is, for example, when the bit address is "4", mask data in which only bits 4 to 7 are "1" is generated by the mask data generator 2002 and stored in the mask data register 3303.

17A and 17B illustrate the basic arithmetic processing executed in the logical address continuous and physical address arithmetic units in the embodiment shown in FIG. 12, and in FIG. 17B, starting from the bit address offset value in each bit mode, this is a bit address. The next offset data register 3205 is generated for the update, and the data of " 4 " in the 4-bit / pixel mode and the data of " 1 " in the 1-bit / pixel mode are generated by the offset generating circuit 2001. To be remembered.

The processing shown in FIG. 17A will be described. This is a process in which the logical address at the point P that represents a certain pixel is represented by (X, Y) and the physical address is represented by PA, and the processing when the point P is moved by ± 1 in the logical address in the horizontal or vertical direction is performed. It is shown. First, when the point P is set to ± 1 to draw pixel data in the X-axis (horizontal direction) forward direction, the source address is read after the data X is read from the current pointer 3 CPX by the logic address calculation unit 310. It is assumed that +1 is added in the calculator 310 through 3109. The calculation result (X + 1) is a new logical address X, which is stored again in the current pointer (CPX of 3102) through the destination latch 3111. At the same time, the physical address calculating unit 320 reads the pointer address from the pointer address register 3208 and gives it to the operator 3202 through the source latch 3204 as operation data. On the other hand, the data from the offset data register 3205 is selectively outputted from the arithmetic data selector 3500 and given to the arithmetic operator 3202 via the source latch 3203 as arithmetic data. Thus, in the calculator 3202, addition is performed between the pointer data PA and the bit address offset value n. This addition result PA + n is a new pointer address which is stored in DPL and DPH of the pointer address register 3208 again through the destination latch 3201. The mask data generator 2002 which generates mask data after this storage generates mask data according to the lower 4 bits of data stored in the pointer address register 3208, that is, the bit address and the bit mode. 3303 is sent to the minimum data calculation section 3305 and provided for the calculation of the pixel data.

In addition, when the point P is moved by +1 in the positive direction of the Y direction (vertical direction), the logical address operation unit 310 similarly performs an operation to +1 the data of the current pointer Y (CPY of 3102). On the other hand, the physical address calculation unit 320 simultaneously calculates the data of the DPL and DPH of the pointer address register 3208. In the calculation in the X direction, the addition and subtraction are performed between the offset values, and in the calculation in the Y direction, the addition and subtraction (in this case, subtraction) is performed between the data from the memory width register 3206. The operation control signal generator generates an addition and a subtraction signal to the calculator 3202 of the physical address calculation unit 320 when the logical address calculation unit 310 adds and operates in the X direction, while the logical address operation unit 310 When addition and subtraction in the Y direction are performed, the subtraction and addition signals are generated for the calculator 3202, but this is determined by the address allocation of the display memory corresponding to the display screen. By performing the above arithmetic processing, the physical address after the movement of the point P is derived. 18 shows an example of linear drawing according to the present invention.

When linear drawing is performed from the starting point P _s (x _s , y _s ) to the end point P _e (x _e , y _e ) of the linear drawing process, the physical address of the origin is first processed as the first preprocessing. A current pointer X (CPX of 3102) and a current pointer Y (CPY of 3102) are set from the micro instruction decoder 200 as a control unit while being set in the DPL, DPH of the address register 3208 from a device or another control device. Cleared to "0" by control. By setting the origin in this way, the correspondence between the logical address and the physical address is taken. Next, as a second preprocess, the logical addresses (x _s , y _s ) of the starting point P _s of the straight line are stored in the current pointers X (CPX) and Y (CPY), respectively, but accordingly the physical address calculation unit 320 The physical address corresponding to the logical address (x _s , y _s ) is obtained. As a third preprocess, the logical addresses (x _e , y _e ) of the end point P _e are stored in the temporal register group 3102, whereby all preprocesses are finished. Then, the micro instruction decoder 200 serving as the control unit starts the processing by receiving a command from the central processing unit or another control device to draw a straight line at the point P _s , but according to the control procedure stored in advance for this processing execution. The control commands are output to the operation units 310, 320, and 330, respectively. In the logical address calculation unit 310, intermediate information necessary for the drawing process such as the inclination of a straight line is obtained from the logical addresses (x _s , y _s ) of the starting point P _s and the logical addresses (x _e , y _e ) of the end point P _e . After being stored in the temporal register group 3102, the calculation of the logical addresses (x ₁ , y ₁ ) of the next drawing point P ₁ and the physical addresses corresponding to the logical addresses (x ₁ , y ₁ ) is calculated according to these data. It is supposed to be done.

Two address operations, a total of an address operation in the X direction and an address operation in the Y direction, are executed by the logical address operation unit 310 and the physical address operation unit 320. In parallel with this, the pixel data corresponding to the starting point P _s is read from the display memory, and the pixel data of the ending point P _e is calculated. After the computation of the pixel data is completed, the pixel data after the computation is rewritten to the display memory. That is, while two memory accesses are executed for a certain point, the logical address operation unit 310 and the physical address are parallel to each other. The calculation unit 320 calculates the logical address for the next drawing point and the corresponding physical address. By repeating this process up to the end point P _e of the straight line, the pixel data for linear drawing is stored in the display memory sequentially.

In addition, the pixel data read out from the display memory is stored in the display memory again in a special case and replaced with constant data. However, in general, pixels existing on a straight line to be drawn are not limited to the same luminance or the same color. Therefore, in such a case, the readout pixel data is stored in the display memory as new pixel data for display, such as a calculation being performed with other data.

In the above embodiment, the logical space is shown in the case of two-dimensional, but it is also applicable to two-dimensional or more.

According to this, even when the pixel data is displayed in plural bits, the logical address and the physical address corresponding to the logical address can be obtained at high speed.

Next, a description will be given of a case where high-speed transfer of pixel information to different pixel positions in a method of storing data of a plurality of pixels in one word of a memory. It is realized by the characteristic hard structure, and high speed processing is attained. For convenience of description, FIG. 19 omits portions of the hard configuration shown in FIGS. 4 to 6 that are not related to the transfer process. The micro instruction decoder 200 includes an address decoder 2002 and a shift amount decoder 2003 within one word. The command control register 230 stores a transfer mode, a bit mode, and the like.

In the display memory 13, addresses are sequentially added in a 16-bit structure. The source address is stored in (T2H, T2L) and the destination address is stored in (DPH, DPL) in the general-purpose register 3208, respectively. That is, the address of the transferred and transmission lines is managed as connecting two registers of a 16-bit structure. The lower four bits of each address information designate a bit position in one word of the memory, and the upper bits designate an address of the display memory.

The shift amount decoder 2003 decodes the shift information to control the shift amount in the barrel shifter 3301. In the transfer process, the difference between the lower 4 bits of the destination address and the source address is an arithmetic logic operator (ALU) ( 3110, and the result is supplied to the shift amount decoder 3002 through a destination latch (DLA) 3111.

The address decoder in one word is temporarily stored in the lower 4 bits of the address information stored in the memory address register 3311 and in the destination latch 3111, corresponding to the bit mode and transfer mode stored in the command control register 230. Based on the information of the difference of the lower four bits of the source address and the destination address, predetermined mask information is generated and sent to the mask data register 3303.

20A and 20B illustrate the operation of the embodiment of FIG. 19. FIG. The case of two transfer modes designated as transfer modes stored in the command control register 230 is shown. 20A shows a case of one pixel transfer mode in which only one pixel of data is transferred at a time. First, the source addresses T2H and T2L are selected, and one word of data including the source pixel is read out from the display memory 13 and sent to the barrel shifter 3301 through the read data buffer 3310. On the other hand, in the arithmetic logic operator 3110, the lower four bits of the source address and the destination address are subtracted, and a shift operation of a plurality of bits is performed by the barrel shifter 3301 through the shift amount decoder 2003. Next, the DPL and DPH of the destination address register 3208 are selected, and a word of data including the destination pixel position is read out and sent to the logical operator 3305 through the read data buffer 3310. On the other hand, the lower 4 bits of the destination address are decoded by the address decoder 2002 in one word, and mask information specifying the destination pixel position is output. In the logical operator 3305, the substitution operation is performed on the output of the barrel shifter 3301 only for the bit position designated by the mask information in the single word data of the destination. The result of this operation is stored in the destination address of the display memory via the write data buffer 3306. By repeating the transfer processing of one pixel while sequentially updating the source address and destination address, a large amount of data can be transferred at high speed regardless of the word boundary of the memory.

20B illustrates the operation of the plural pixel transfer mode. In this case, the address decoder 2002 sets " 1 " to a plurality of bit positions in accordance with the specification of the transfer mode bit in the register 230. FIG. Therefore, it is possible to further speed up when transmitting a plurality of horizontally continuous bits.

As described above, according to the present embodiment, even when a plurality of pixels of data are stored in one word of the display memory, three or more memory accesses of source reading, destination reading and destination writing are performed for one or a plurality of arbitrary pixel positions. Pixel data can be transferred, and high-speed transfer is possible. By the GBM of the register 230, for example, five different operation modes (see FIG. 8) can be selected.

21 shows transmission of one pixel data in the case of 4 bit / 1 pixel mode. A process of reading one word data included in the source pixel and embedding only the source pixel data in the destination pixel position is necessary.

22 shows the flow of the transfer process. First, one word of the display memory 13 including the source pixel is read out and temporarily stored in the read data buffer 3310. On the other hand, the lower four bits of the address information specifying the source pixel and the lower four bits of the address specifying the destination pixel are subtracted. This value represents the difference between the bit position of the source pixel and the destination pixel. The source read data is shifted to the barrel shifter 3301, and the source pixel C _s is adjusted to the position of the destination pixel. Subsequently, one word including the destination pixel C _d is read out, and a calculation with the source pixel C _s is performed by the logic operator 3305. At this time, since "1" is generated only at the destination pixel position as the mask information, only one pixel of the destination is updated to obtain write data. Types of logical operations may be substituted, logical operations, and the like. Also in the case of the 4 bit / pixel mode, only the format of the mask information is different, and the same operation is performed at all.

As described above, according to the present embodiment, even when data of one pixel is displayed with a plurality of bits, the pixel data can be transferred to any pixel position by three memory accesses of source read, destination read, and destination write. There is an effect.

FIG. 23 shows a pointer movement direction SD of a transfer command when a quadrangular region is designated as an example of pixel data transfer, and shows eight kinds of a to h. Source area and destination area can be specified independently.

Next, arithmetic control in which the calculation of the pixel position in the transfer is easy will be described.

FIG. 24 particularly shows a part related to the operation control of the pixel position based on the configuration shown in FIG. In the flag register 210, a code decoder 2101 and a code register 2102 are incorporated. The flag register 210 has an area determination flag, a zero flag, a negative flag, and the like, which are reflected depending on the state of the calculation result. However, the flag register 210 is not shown here because it is not used for the description.

In the command register 3207, command codes in commands transmitted from the outside through the FIFO memory 400 are temporarily stored. A part of the information of the command code is transmitted to the microprogram address register 110 so that the microprogram is sequentially read out and operation control is performed according to a predetermined processing algorithm.

The arithmetic and control unit 300 executes coordinate calculation for calculating the drawing address of the figure and processing of the figure data. The code decoder 2101 generates predetermined code data according to the present invention in accordance with some information of the command code and information provided from other components in the computing device 30.

The code register 2102 temporarily stores the code data generated by the code decoder 2101. The mode decoder 2009 disposed in the microinstruction decoder 200 decodes the processing mode field of the command to control arithmetic processing.

25a to e show the format (CDT) of the nosebleed (transfer) command. It consists of a command code of 1 word (16 bits) and the following parameters 1 to 4 of 4 words. By setting the parameters, various scanning directions can be selected during transmission.

Fig. 26 shows a conceptual diagram of an operation example of the kopi command. The parameters X _s and Y _s are starting point coordinates of the source (transmission source) area 13S. The parameters DX, DY define the direction and size of the area. That is, starting from X _s and Y _s , the area is moved in the right direction in FIG. 25 when DX> 0, the left direction when DX <0, the upward direction when DY> 0, and the downward direction when DY <0. And specify the size in absolute values of DX and DY. The S bit in FIG. 25A indicates the priority scan priority, and the priority in the horizontal direction when S = 0 and the vertical direction when S = 1.

In the embodiment of Fig. 24, the first word among commands transmitted from the outside is recognized as a command code and is dimensioned to the command register 3207. The microprogram is started in accordance with the upper four bits of the command code to start the control of the nose copy processing.

The S bit and the DSD field (Fig. 25) in the command code are sent to the code register 2102 via the code decoder 2101. The lower processing mode field of the command code is decoded by the mode decoder 2009.

The parameters 1 to 4 are sent to a register 3102 in the arithmetic operation control device 300 in sequence. The drawing point coordinates (X, Y) of the shape member are stored in the registers CPX, CPY.

27A is a layout diagram showing an example of the structure of a code register 2102 according to the present invention. This code register holds the next 10 bits of information. In addition, in this figure, the information stored in each register part is shown by the arrow, respectively, taking the case of the kopi command as an example.

(1) Q1

It is a 1st bit which switches between coordinate registers X and Y. In the copi command, it is used to determine the priority in the X-direction and Y-direction of scanning in the source region 13S. Therefore, the S bit of the command code is set as Q1.

When Q1 = 0, the X and Y registers are selected as specified. When Q1 = 1, the Y register is selected when X is specified and the X register when Y is specified.

(2) Q2

The second bit for switching the coordinate registers X and Y. In the copi command, it is used to switch between the X and Y directions of scanning in the destination region 13D. Therefore, bit 2 of the DSD field (Fig. 25) of the command code is set as Q2.

When Q2 = 0, the X and Y registers are selected as specified, and when Q2 = 1, the registers are selected by reversing the X and Y specifications.

(3) S1x

Two bits of information are held for the operation code in the first X direction. In general, the upper bit of the two bits is for selecting whether to add or subtract, and the lower bit to add or subtract (when the bit is "1") or not (bit is "0"). Is to make a choice).

In the Kopi command, the sign of the parameter DX is set in the upper bit, and "1" is set in the lower bit. In other words, the upper bits are used as information specifying an operation code in the X direction of the source region 13S.

(4) S1y

Two bits of information that hold the operation code in the first Y-direction, and are used for operation selection as in the above-described S1x.

In the kopi command, the sign (high bit) and "1" (low bit) of the parameter DY are set, respectively, and the operation code in the Y direction of the source area 13S is designated.

(5) S2x

Two bits of information that hold the second operation code in the X direction, and the operation code in the X direction of the destination area D is designated in the Copi command. Bit 1 of the DSD field of the command is set higher and "1" is lower.

(6) S2y

Two bits of information that hold the operation code in the second Y direction, and the operation code in the Y direction of the destination area D is designated in the Copi command. Bit 1 of the DSD field of the command is set higher and "1" is lower.

Summarizing the above, all of the lower bits of S1x, S1y, S2x, and S2y are set to "1". However, the command for performing other processing may control and change this bit.

28 shows a processing flow of the kopi command. The contents of the expression specifying each register are as follows.

(1) X _s (Q1)

Specify the X _s register when Q1 = 0 and the Y _s register when Q1 = 1. That is, it is the coordinate value of the 1st or preferential scanning direction of the source area 13S.

(2) Y _s (Q1)

Specify the Y _s register when Q1 = 0 and the X _s register when Q1 = 1. That is, it is the coordinate value of the 2nd scanning direction of the source area 13S.

(3) X (Q2)

Specify the X register when Q2 = 0 and the Y register when Q2 = 1. That is, it is the coordinate value of the 1st or preferential scanning direction of the destination area | region 13D.

(4) Y (Q2)

Specify the Y register when Q2 = 0 and the X register when Q2 = 1. That is, it is the coordinate value of the 2nd scanning direction of the source area | region 13D.

(5) S1x (Q1)

Select S1x at Q1 = 0 and S1y at Q1 = 1. That is, it is the code | symbol of the 1st (priority) scanning direction of the source area 13S.

(6) S1x (Q1)

Select S1y at Q1 = 0 and S1x at Q1 = 1. That is, it is the code | symbol of the 2nd scanning direction of the source area | region 13S.

(7) S2x (Q2)

Select S2x at Q2 = 0 and S2y at Q2 = 1. That is, it is the code | symbol of the 1st (priority) scanning direction of the destination area | region 13D.

(8) S2y (Q2)

Select S2y at Q2 = 0 and S2x at Q2 = 1. That is, it is the sign of the 2nd scanning direction of the destination area | region 13D.

In Fig. 28, in the first command code, parameters 1 to 4 following the command code, that is, X _s , Y _s , DX, and DY are sequentially input and stored in a register inside the operation control device 300. (Step S1) .

Subsequently, processing for one line in the first (priority) scanning direction is started. To this end, the starting coordinate values in the first (first) scanning direction of X _s (Q1) and X (Q2), that is, source region 13S and destination region 13D, are saved (temporarily stored) in another register (step). S2).

Next, the pixel information of the coordinate point designated by (X _S , Y _S ) is transferred to the coordinate point designated by (X, Y) (step S3). Such transfer processing of one pixel is as described above.

Next, the code values S1x (Q1) and S2x (Q2) are added to the coordinate values X _S (1) and X (Q2) in the first scanning direction of the source region 13S and the destination region 13D. That is, the designated coordinate points of the respective areas are moved by one pixel in the first scanning direction, respectively (step S4).

The processing of steps S3 and S4 is repeated until the designated coordinate point reaches the end point of one line (step S5).

When the processing of one line is finished and the determination at step S5 is satisfied, X _s , (Q1), and X (Q2) are returned (step S6), and the second scanning direction coordinate values Y _s (Q1), Y _s ( The code values S1y (Q1) and S2y (Q2) are added to Q2), respectively, and the starting point coordinates of the second line are set (step S7).

By repeating the above-described processes of steps S2 to S7 until the determination of step S8 is satisfied until the entire line processing in the second scanning direction is completed, the transfer of all data in the source area 13S can be executed.

As described above, in the present embodiment, various pointer scanning modes at the time of area data transfer can be realized in a single processing flow shown in FIG. 28, so that the control information (e.g., microprogram) can be greatly reduced or simplified. Can be.

Further, other commands and pattern commands can be applied similarly.

27b and c show the format of pattern commands. As apparent from the figure, this command is configured as a command code of one word and 16 bits and a parameter of one word.

The pattern command is a command that expands the pattern information stored in the pattern memory inside the figure processing apparatus onto the display memory. By selecting the command operation mode, the pointer can be subjected to various scans.

Claims (24)

A graphic processing apparatus for accessing a display memory 13 having a plurality of bits of one pixel data and having a plurality of the pixel data as an access unit, comprising: a memory address of a word of the display memory and the memory address designated by the memory address; A physical address operation unit 320 for calculating position information of a drawing point including a pixel address defining a pixel position within one word, and a color data operation unit 330 for updating pixel data designated by the pixel address in accordance with a drawing command. Shape processing apparatus characterized in that it has a. A graphic processing apparatus for accessing a display memory 13 having a plurality of bits of one pixel data and having a plurality of the pixel data as an access unit, comprising: a memory address of a word of the display memory and the memory address designated by the memory address; A physical address operation unit 320 for calculating position information of a drawing point including a pixel address defining a pixel position in a word, and a color data operation unit 330 for updating pixel data designated by the pixel address in accordance with a drawing command. And a control device 20 for decoding the given drawing command to control the drawing function, a command control register 230 for supplying a drawing command given to the control device at least, and a pattern memory for storing the graphic pattern data ( 220 and information output means 40, 50 for outputting an image of the graphic pattern data stored in the pattern memory. Figure processing apparatus, characterized in that. Information output means (40,50) for outputting an image of graphic pattern data; a display memory (13) comprising a plurality of bits of one pixel data; And a graphics processing unit (20, 30) including an arithmetic unit (30) for writing to an address of a display memory and a control unit (20) for designating respective pixel data of a plurality of pixel data indicated by the address. Figure processing apparatus, characterized in that. 4. The figure processing apparatus according to claim 3, further comprising an operation unit (30) for updating pixel data to be written in an address of said display memory (13). 4. The graphics processing device according to claim 3, wherein the control device (20) designates information about the content of each word including a plurality of pixels stored in the display memory (13). Information output means (40,50) for outputting an image of graphic pattern data, a display memory (13) comprising a plurality of bits of one pixel data, and the plurality of pixel data as an access unit, and a memory in the display memory An associating device 30 which designates predetermined pixel data among the plurality of pixel data designated by the address by the pixel address, and writes the designated pixel data into the display memory, and the number of bits constituting the one pixel data. Shape processing apparatus characterized in that it has a control device for changing the (20). Information output means (40,50) for outputting an image of graphic pattern data, a display memory (13) consisting of a plurality of bits of one pixel data, the plurality of pixel data being an access unit, and each pixel at least An arithmetic unit 30 for writing at least one pixel of data having one bit into a word address of the display memory, and a controller 20 for designating a variable of pixel data to be written in a word address of the display memory. Figure processing apparatus characterized in that it has. Information output means (40,50) for outputting an image of graphic pattern data, a display memory (13) having a plurality of bits of one pixel data, and the plurality of pixel data as access units, and each pixel being selected And a graphics processing apparatus (20, 30) for writing data of a plurality of pixels whose variable bits in a word can be written into an address of the display memory. Outputting an image of the graphic pattern data; storing at least one pixel as an image element of a unique point in a two-dimensional space of the graphic pattern data in an address supplied by the pixel to the output of the image of the graphic pattern data; And a step of designating the number of bits of data stored in at least one pixel and the step of writing at least one pixel of data in a word with the number of bits in the specified number of at least one pixel. How to operate. Generates graphic data, which is stored as a plurality of pixel data per word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory storing the pixel data. A graphics processing apparatus (20,30) selectable to store information, comprising: drawing point information including a memory address of a word in the display memory and a pixel address defining a position of a pixel in one word designated by the memory address, And a specific pixel in one word specified by the pixel address in accordance with a drawing command. Generates graphic data, which is stored as a plurality of pixel data per word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory storing the pixel data. Selectable, and store drawing point information including a memory address of a word in the display memory and a pixel address defining a position of a pixel in one word designated by the memory address, and storing the drawing point information by the pixel address in accordance with a drawing command. And updating a specific pixel within a designated word. Generates graphic data, which is stored as a plurality of pixel data per word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory storing the pixel data. Selectable to store drawing point information including a memory address of a word in the display memory and a pixel address defining a position of a pixel in one word designated by the memory address, and storing the drawing point information by the pixel address in accordance with a drawing instruction. A stretching device 30 for updating a specific pixel within a designated word, a control device 20 for decoding a given drawing command to control a drawing function, and an external calculator for giving at least one drawing command to the control means. And a display conversion device 40 for outputting an image of the graphic pattern stored in the display memory. Geometry processing apparatus as. Generates graphic data, which is stored as a plurality of pixel data per word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory storing the pixel data. A graphics processing apparatus selectable to store information, comprising: drawing point information including a memory address of a word in the display memory and a pixel address defining a position of a pixel in one word designated by the memory address, and storing the drawing point information in accordance with a drawing instruction. Update a specific pixel in one word designated by the pixel address, decode the given drawing command to control the drawing function, give at least one drawing command, and display the image of the graphic pattern stored in the display memory. Figure processing apparatus characterized in that the output. Generates graphic data, which is stored as a plurality of pixel data per word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory storing the pixel data. Selectable to write data of a plurality of pixels, each pixel having at least one bit, to an address of the display memory, and to specify a position of a pixel of each word of data to be written to an address position of the display memory. Figure processing apparatus, characterized in that. 15. The graphic processing apparatus according to claim 14, further comprising an arithmetic unit (30) for updating pixel data to be written in an address of said display memory (13). Generates graphic data, which is stored as a plurality of pixel data per word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory storing the pixel data. Select the pixel number of each word of data to be written at an address of the display memory and writing data of a plurality of pixels each pixel having at least one bit to the address of the display memory. Figure processing device characterized in that. 17. The graphic processing apparatus according to claim 16, wherein the pixel data to be written at the address position of the display (13) is updated. Generates graphic data, which is stored as a plurality of pixel data per word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory storing the pixel data. A graphics processing apparatus selectable so that a pixel position specified by a memory address in a display memory has at least one pixel, and at least one pixel position designated by a pixel address of a word position in a display memory. And a minimum number of pixel data in the word position, and specifying the number of pixel data to be written in the word position and the pixel address in the word position. Generates graphic data, which is stored as a plurality of pixel data per word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory storing the pixel data. At least one pixel word position in which the pixel specified by the memory address in the display memory has at least one bit and at least one pixel position specified by the pixel address of the word position in the display memory. And specify the number of pixel data to be written in the word position and the pixel address in the word position. Graphic data is generated, and this graphic data is stored as a plurality of pixel data for each word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory for storing the pixel data. At least one pixel word position in which the pixel specified by the memory address in the display memory has at least one bit and at least one pixel position specified by the pixel address of the word position in the display memory. And a control device (20) for specifying the number of pixel data to be written in the word position and the pixel address in the word position. Generates graphic data, which is stored as a plurality of pixel data per word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory storing the pixel data. A graphics processing apparatus which can be selected so as to write data of a plurality of pixels included in a word in which a variable of a pixel is to be selected at an address position of the display memory. Graphic data is generated, and this graphic data is stored as a plurality of pixel data for each word in the display memory 13, and the number of pixels in each word of the pixel data accesses the display memory for storing the pixel data. And write data of a plurality of pixels included in a word in which a variable of the pixel is to be selected at an address position of the display memory. A graphic processing apparatus for accessing a display memory 13 having a plurality of bits of one pixel data and having a plurality of pixel data as an access unit, comprising: a memory address of a word in the display memory and the memory address; A physical address operation unit 320 for storing drawing point information including a pixel address defining a pixel position within a specified word, and a color data calculating unit for updating a specific pixel in one word specified by the pixel address in accordance with a drawing command. Figure 330 is characterized in that it has a. A graphic processing apparatus for accessing a display memory 13 having a plurality of bits of one pixel data and having a plurality of pixel data as an access unit, comprising: a memory address of a word in the display memory and the memory address; A physical address operation unit 320 for generating drawing point information including a pixel address defining a pixel position within a specified one word, and a color data calculating unit for updating a specific pixel in one word specified by the pixel address in accordance with a drawing command. 330, a control device 20 for decoding the given drawing command to control the drawing function, command memory 230 and 400 for supplying at least one drawing command to the control device, and a pattern for storing graphic pattern data. Memory 220 and information output means (40, 50), (3400) for outputting an image of a graphic pattern stored in the pattern memory. Shape processing apparatus.