KR940009976A - Cross Interleave Method and Circuit - Google Patents
Cross Interleave Method and Circuit Download PDFInfo
- Publication number
- KR940009976A KR940009976A KR1019920019825A KR920019825A KR940009976A KR 940009976 A KR940009976 A KR 940009976A KR 1019920019825 A KR1019920019825 A KR 1019920019825A KR 920019825 A KR920019825 A KR 920019825A KR 940009976 A KR940009976 A KR 940009976A
- Authority
- KR
- South Korea
- Prior art keywords
- address
- cross
- encoding
- output
- interleave
- Prior art date
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
- G11B7/08—Disposition or mounting of heads or light sources relatively to record carriers
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- Error Detection And Correction (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
크로스인터리브방법 및 회로는 어드레스를 출력데이터를 기준으로 하여 발생시켜 사용되는 메모리의 용량 및 입출력데이터레이트의 차이를 보상해주고, 또한 각 채널마다 실질적으로 사용되는 메모리의 용량을 감소시키기 위한 것이다.The cross-interleave method and circuit are designed to compensate for the difference between the memory capacity and the input / output data rate used by generating an address based on the output data, and to reduce the capacity of the memory that is substantially used for each channel.
이를 위하여 엔코딩시스템에서 출력되는 출력데이터를 기준으로 하여 각 채널에 대하여 크로스인터리브규칙에 따른 출력데이터와P엔코딩 어드레스와 Q엔코딩 어드레스 발생간의 소정의 지연량만큼 지연된 Q엔코디어드레스를 발생하며, 발생된 어드레스에 크로스인터리브규칙에 따른 Q엔코딩어레스와 입력데이터간에 소정의 지연량 및 섞임에 의하여 입력데이터의 어드레슬?? 얻기 위한 과정으로 이루어진다. 또한 크로스인터리부를 콘트롤러에서 출력되는 싱크신호를 카운트하기 위한 싱크카운터, 콘트롤러에서 출려고디는 데이터구간(DATATIME) 신호에 의하여 클리어되고 심보를럭신호를 카운트하기 위한 심볼카운터, 크로스인터리브를 위한 엔코딩데이터 및 입력 및 출력데이터들을 별도로 저장하고 심볼카운터에서 출력되는 신호에 해당되는 어드레스를 동시에 발생하기 위한 적어도 1개 이상의 메모리, 상기 콘트롤러에서 출력되는 선택제어신호에 의하여 상기 메모리에서 발생되는 어드레스중 해당되는 데이터의 어드레스만을 선택하여 출력하기위한 선택수단, 선택수단에서 출력되는 데이터와 싱크카운터에서 출력되는 신호를 가산하여 크로스인터리브를 위한 어드레스를 메모리로 출력하기 위한 가산기로 재구성하고, 엔코딩시스템의 출력신호를 기준으로 하여 크로스인터리브규칙에 따른 지연량에 의하여 각 채널에 해당되는 엔코딩값을 설정하고, 설정된 값간의 차에 의하여 각 채널에 할당되는 메모리 영역을 가변적으로 설정하기 위한 과정으로 이루어진다.To this end, for each channel, based on the output data output from the encoding system, the output data according to the cross-interleave rule and the Q encoding address delayed by a predetermined delay amount between the generation of the P encoding address and the Q encoding address are generated. The address of the input data by a predetermined amount of delay and mixing between the Q encoding address and the input data according to the cross-interleave rule at the address ?? It is a process to obtain. In addition, the sync counter for counting the sync signal output from the controller, the counter counter for counting the symbolic luck signal, cleared by the DATATIME signal from the controller, and encoding for the cross interleave. At least one memory for storing data and input and output data separately and simultaneously generating an address corresponding to a signal output from a symbol counter, and a corresponding one of addresses generated in the memory by a selection control signal output from the controller Selecting means for selecting and outputting only the address of the data, adding the data output from the selecting means and the signal output from the sink counter, reconfiguring with an adder for outputting the address for the cross-interleave into memory, and outputting the output signal of the encoding system. group As to comprises a process to variably set a memory area allocated to each channel by a difference between the set value to be encoded for each channel by the delay amount, and set the value of the cross-interleaving rule.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제9도는 본 발명에 따른 제2도의 프레임테이블과 옵셋테이블의 내용이다,9 is the contents of the frame table and offset table of FIG. 2 according to the present invention.
제10도는 본 발명에 따른 크로스인터리브회로의 다른 실시예이다,10 is another embodiment of a cross-interleave circuit according to the present invention.
제11도는 제10도에 따른 롬1~롬4의 내용이다.FIG. 11 shows the contents of Romans 1 to 4 according to FIG. 10.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920019825A KR0123766B1 (en) | 1992-10-27 | 1992-10-27 | Cross interleaing method and its circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920019825A KR0123766B1 (en) | 1992-10-27 | 1992-10-27 | Cross interleaing method and its circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940009976A true KR940009976A (en) | 1994-05-24 |
KR0123766B1 KR0123766B1 (en) | 1997-11-27 |
Family
ID=19341831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920019825A KR0123766B1 (en) | 1992-10-27 | 1992-10-27 | Cross interleaing method and its circuit |
Country Status (1)
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KR (1) | KR0123766B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100910484B1 (en) * | 2002-11-12 | 2009-08-04 | 주식회사 포스코 | An apparatus for supporting a strip trimmed by a side trimmer |
-
1992
- 1992-10-27 KR KR1019920019825A patent/KR0123766B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100910484B1 (en) * | 2002-11-12 | 2009-08-04 | 주식회사 포스코 | An apparatus for supporting a strip trimmed by a side trimmer |
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Publication number | Publication date |
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KR0123766B1 (en) | 1997-11-27 |
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