KR940009850A - Data input / output method in multiprocessor system - Google Patents

Data input / output method in multiprocessor system Download PDF

Info

Publication number
KR940009850A
KR940009850A KR1019920019182A KR920019182A KR940009850A KR 940009850 A KR940009850 A KR 940009850A KR 1019920019182 A KR1019920019182 A KR 1019920019182A KR 920019182 A KR920019182 A KR 920019182A KR 940009850 A KR940009850 A KR 940009850A
Authority
KR
South Korea
Prior art keywords
bus
data
signal
mode
output method
Prior art date
Application number
KR1019920019182A
Other languages
Korean (ko)
Inventor
김용
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019920019182A priority Critical patent/KR940009850A/en
Publication of KR940009850A publication Critical patent/KR940009850A/en

Links

Landscapes

  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

본 발명은 다중 프로세서 시스템의 데이타 입출력 방법에 관한 것으로, 종래에는 특정 마이크로 프로세서가 버스를 점유하지 못하게 하여 동작수행을 향상시키나 프로그램 특성상 인접 어드레스나 프로세서에서 버스를 점유하고 데이타 전송에 지장을 초래하는 문제점이 있었다. 이러한 점을 감안하여 본 발명에서는 버스이 대역폭(Bond Width)을 변경함이 없이 마이크로 프로세서의 버스 사용을 제어함으로써 연속적인 데이타를 전송하고 캐쉬 블럭의 크기를 변경하여 시스템의 성능을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input / output method of a multiprocessor system. In the related art, it is possible to prevent a specific microprocessor from occupying a bus, thereby improving operation performance. There was this. In view of this, the present invention can improve the performance of the system by transferring data continuously and changing the size of the cache block by controlling the bus usage of the microprocessor without changing the bandwidth of the bus.

Description

다중 프로세서 시스템의 데이타 입출력 방법Data input / output method in multiprocessor system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에서 데이타 입출력에 따른 상태도,2 is a state diagram according to data input and output in the present invention,

제3도는 본 발명에 따른 데이타 입출력시 타이밍도,3 is a timing diagram of data input / output according to the present invention;

제4도는 본 발명에 따른 데이타 입출력시 신호 흐름도.4 is a signal flow diagram for data input and output according to the present invention.

Claims (2)

데이타 전송에 따른 모드 판별시 리드 모드일 때 버스트 모드이면 버스트신호(Bur)를 출력하고 데이타 인식신호(AACK) 및 버스 사용 억제 신호(ABimh)가 입력됨에 따라 데이타(Data)를 읽는 제1단계와, 제1단계에서 리드모드가 아닐 때 라이드 모드이면 버스트 모드인지 판별하는 제2단계와, 제2단계에서 버스트 모드이면 버스트 신호(Bur) 및 버스 사용 억제 신호(ABinh)를 출력하고 버스(Bus)가 비지(Busy)상태가 아님과 동시에 버퍼가 빈(empty)상태에 따른 어드레스 인식신호(AACK)가 입력되면 데이타를 메모리에 저장하는 제3단계로 이루어진 것을 특징으로 하는 다중 프로세서 시스템의 데이타 입출력방법.The first step of outputting the burst signal Bur in the read mode and reading the data as the data recognition signal AACK and the bus use suppression signal ABimh are input when the mode is determined according to the data transmission. In the first step, if the Ride mode is not in the read mode, the second step of determining whether the burst mode; if the burst mode in the second step, outputs the burst signal Bur and the bus use suppression signal ABhinh and outputs the bus Bus. Data input / output method of a multi-processor system comprising the step of storing data in memory when the address recognition signal (AACK) is inputted while the buffer is not busy and the buffer is empty. . 제1항에 있어서, 데이타 전송시 버스 사용 억제 신호(ABinh)를 출력하여 다른 프로세서와 버스 사용을 억제함으로써 데이타 버스의 충돌을 방지하는 것을 특징으로 하는 다중 프로세서 시스템의 데이타 입출력방법.The data input / output method of a multiprocessor system according to claim 1, wherein a collision of a data bus is prevented by outputting a bus use inhibit signal ABinh during data transfer to suppress the use of a bus with another processor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920019182A 1992-10-19 1992-10-19 Data input / output method in multiprocessor system KR940009850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920019182A KR940009850A (en) 1992-10-19 1992-10-19 Data input / output method in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920019182A KR940009850A (en) 1992-10-19 1992-10-19 Data input / output method in multiprocessor system

Publications (1)

Publication Number Publication Date
KR940009850A true KR940009850A (en) 1994-05-24

Family

ID=67210226

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920019182A KR940009850A (en) 1992-10-19 1992-10-19 Data input / output method in multiprocessor system

Country Status (1)

Country Link
KR (1) KR940009850A (en)

Similar Documents

Publication Publication Date Title
KR100337056B1 (en) Buffering data that flows between buses operating at different frequencies
US6253297B1 (en) Memory control using memory state information for reducing access latency
KR890005739A (en) Bus master with selected delay burst
US5634139A (en) Microprocessor using feedback memory address to internally generate bust mode transfer period signal for controlling burst mode data transfer to external memory
US7062588B2 (en) Data processing device accessing a memory in response to a request made by an external bus master
US5826108A (en) Data processing system having microprocessor-based burst mode control
KR0155044B1 (en) Ram data transferring apparatus using fifo memory and its method
KR940009850A (en) Data input / output method in multiprocessor system
KR100190184B1 (en) Transmitting circuit for data with serial bus line
KR950024080A (en) Cache Data Transmitter in Multiprocessor System
KR960042391A (en) DM controller in high speed medium computer system
KR970020450A (en) Printer
JP2806405B2 (en) Microprocessor
KR100283187B1 (en) Device and method for accessing common memory in system using common memory
JPH06325570A (en) Dynamic memory refresh circuit
KR950020205A (en) Buffer RAM Controller for Dual Port Support and VME Interface
KR920006860A (en) Multi-Process System Arbiter Delay Circuit
JP2966038B2 (en) Digital data processing unit arbitration apparatus and method
JPS6269347A (en) Direct memory access controller
JPS6159563A (en) Bus control system
JPS63191398A (en) Information processor
JPS61120396A (en) Microprocessor
KR950020184A (en) Common Memory Access Control Circuit in Multiprocessor System
KR930002949A (en) High Speed SCSI Host Adapter
JPH0675905A (en) Bus conversion system

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination