KR940009850A - Data input / output method in multiprocessor system - Google Patents
Data input / output method in multiprocessor system Download PDFInfo
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- KR940009850A KR940009850A KR1019920019182A KR920019182A KR940009850A KR 940009850 A KR940009850 A KR 940009850A KR 1019920019182 A KR1019920019182 A KR 1019920019182A KR 920019182 A KR920019182 A KR 920019182A KR 940009850 A KR940009850 A KR 940009850A
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- South Korea
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- bus
- data
- signal
- mode
- output method
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- Memory System Of A Hierarchy Structure (AREA)
Abstract
본 발명은 다중 프로세서 시스템의 데이타 입출력 방법에 관한 것으로, 종래에는 특정 마이크로 프로세서가 버스를 점유하지 못하게 하여 동작수행을 향상시키나 프로그램 특성상 인접 어드레스나 프로세서에서 버스를 점유하고 데이타 전송에 지장을 초래하는 문제점이 있었다. 이러한 점을 감안하여 본 발명에서는 버스이 대역폭(Bond Width)을 변경함이 없이 마이크로 프로세서의 버스 사용을 제어함으로써 연속적인 데이타를 전송하고 캐쉬 블럭의 크기를 변경하여 시스템의 성능을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data input / output method of a multiprocessor system. In the related art, it is possible to prevent a specific microprocessor from occupying a bus, thereby improving operation performance. There was this. In view of this, the present invention can improve the performance of the system by transferring data continuously and changing the size of the cache block by controlling the bus usage of the microprocessor without changing the bandwidth of the bus.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에서 데이타 입출력에 따른 상태도,2 is a state diagram according to data input and output in the present invention,
제3도는 본 발명에 따른 데이타 입출력시 타이밍도,3 is a timing diagram of data input / output according to the present invention;
제4도는 본 발명에 따른 데이타 입출력시 신호 흐름도.4 is a signal flow diagram for data input and output according to the present invention.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920019182A KR940009850A (en) | 1992-10-19 | 1992-10-19 | Data input / output method in multiprocessor system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920019182A KR940009850A (en) | 1992-10-19 | 1992-10-19 | Data input / output method in multiprocessor system |
Publications (1)
Publication Number | Publication Date |
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KR940009850A true KR940009850A (en) | 1994-05-24 |
Family
ID=67210226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019920019182A KR940009850A (en) | 1992-10-19 | 1992-10-19 | Data input / output method in multiprocessor system |
Country Status (1)
Country | Link |
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KR (1) | KR940009850A (en) |
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1992
- 1992-10-19 KR KR1019920019182A patent/KR940009850A/en not_active Application Discontinuation
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