KR940009845A - Security circuit - Google Patents

Security circuit Download PDF

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Publication number
KR940009845A
KR940009845A KR1019930022480A KR930022480A KR940009845A KR 940009845 A KR940009845 A KR 940009845A KR 1019930022480 A KR1019930022480 A KR 1019930022480A KR 930022480 A KR930022480 A KR 930022480A KR 940009845 A KR940009845 A KR 940009845A
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KR
South Korea
Prior art keywords
circuit
security
data
signal
supplied
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Application number
KR1019930022480A
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Korean (ko)
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KR960006485B1 (en
Inventor
슈지 하야시
Original Assignee
사토 후미오
가부시키가이샤 도시바
오카모토 세이시
도시바 마이크로일렉트로닉스 가부시키가이샤
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Publication of KR940009845A publication Critical patent/KR940009845A/en
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Publication of KR960006485B1 publication Critical patent/KR960006485B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Microcomputers (AREA)

Abstract

본 발명은 시큐리티를 설정한 것을 다른 사람은 바로 알 수 없으므로, 메모리에 기억된 데이터를 확실히 보호하는 것이 가능한 시큐리티회로를 제공하고자 함에 그 목적이 있다. 이를 위해 본 발명에서는, 메모리(2)에는 시큐리티 데이터가 기억되고, 래치회로(4)에는 키데이터가 래치된다. 비교회로(6)에 의해 시큐리티 데이터와 키데이터가 일치하지 않는다고 판단되면, 변경비트 제어회로(20)의 출력신호(S13)는 "O"레벨로 되어 어드레스 변경회로(301∼30n)에 공급되는 어드레스신호는 메모리(2)로부터 공급되는 시큐리티 데이터에 따라 변환된다. 따라서, 이 어드레스 신호에 의해 메모리(1a)는 엑세스되지만 정상적인 데이터는 출력되지 않는다.An object of the present invention is to provide a security circuit capable of reliably protecting data stored in a memory because no other person can immediately know that security has been set. To this end, in the present invention, the security data is stored in the memory 2, and the key data is latched in the latch circuit 4. By the comparison circuit 6, when determining that the security data and key data do not match, the change bit control signal output (S 13), the address changing circuit (30 1 ~30 n) is at the "O" level of the circuit 20 The address signal supplied to is converted in accordance with the security data supplied from the memory 2. Therefore, the memory 1a is accessed by this address signal, but normal data is not output.

Description

시큐리티회로Security circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 제1실시예를 나타낸 구성도,1 is a block diagram showing a first embodiment of the present invention,

제2도는 본 발명의 제2실시예를 나타낸 주요부의 구성도.2 is a block diagram of an essential part showing a second embodiment of the present invention.

Claims (6)

기밀을 유지해야 할 데이터를 기억하는 제1기억수단(1a)과, 시큐리티 데이터를 기억하는 제2기억수단(2), 상기 시큐리티 데이터에 의해 설정된 시큐리티를 해제하기 위한 키데이터를 래치하는 래치회로(4), 상기 제2기억수단(2)에 기억되어 있는 시큐리티 데이터와 상기 래치회로(4)에 의해 래치된 키데이터를 비교하여 이들이 일치하고 있는 경우에는 일치신호를 출력하고, 이들이 일치하지 않는 경우에는 불일치신호를 출력하는 비교회로(6) 및 상기 제1기억수단(1a)에 기억되어 있는 데이터를 독출하기 위한 어드레스신호 및 상기 비교회로(6)의 출력신호가 공급되어 이 비교회로(6)로부터 불일치신호가 공급된 경우에는 상기 어드레스신호를 변화시키고, 일치신호가 공급된 경우에는 상기 어드레스신호를 그대로 출력하는 어드레스 제어회로(301∼30n)를 구비한 것을 특징으로 하는 시큐리티회로.A latch circuit for latching first storage means 1a for storing data to be kept confidential, second storage means 2 for storing security data, and key data for releasing the security set by the security data ( 4) When the security data stored in the second storage means 2 and the key data latched by the latch circuit 4 are compared, and if they match, a matching signal is outputted, and they do not match. A comparison circuit 6 for outputting a mismatch signal, an address signal for reading data stored in the first storage means 1a, and an output signal of the comparison circuit 6 are supplied to the comparison circuit 6. The address control circuits 30 1 to 30 n which change the address signal when a mismatch signal is supplied from the circuit and output the address signal as it is when the match signal is supplied. A security circuit comprising: 제1항에 있어서, 상기 어드레스 제어회로는 어드레스신호, 상기 시큐리티 데이터 및 상기 비교회로(6)의 출력신호가 각각 공급되는 복수개의 어드레스 변경회로(301∼30n)을 갖추며, 이들 어드레스 변경회로(301∼30n)는 상기 비교회로(6)로부터 불일치신호가 공급된 경우에 상기 시큐리티 데이터에 따라 어드레스신호를 변화시키도록 되어 있는 것을 특징으로 하는 시큐리티회로.2. The address control circuit according to claim 1, wherein the address control circuit includes a plurality of address change circuits 30 1 to 30 n to which an address signal, the security data, and an output signal of the comparison circuit 6 are respectively supplied. (30 1 to 30 n ) are configured to change an address signal in accordance with the security data when an inconsistency signal is supplied from the comparison circuit (6). 제2항에 있어서, 상기 각 어드레스 변경회로(301∼30n)는 상기 어드레스신호를 임의로 변화시키는 스크램블 회로(32)를 포함하는 것을 특징으로 하는 시큐리티회로.3. The security circuit according to claim 2, wherein each address changing circuit (30 1 to 30 n ) includes a scramble circuit (32) for arbitrarily changing the address signal. 제3항에 있어서, 상기 스크램블회로(32)는 어드레스신호를 변화시키는 복수개의 인버터회로(32a,32b)를 포함하고 있는 것을 특징으로 하는 시큐리티회로.4. The security circuit according to claim 3, wherein said scramble circuit (32) includes a plurality of inverter circuits (32a, 32b) for changing an address signal. 제3항에 있어서, 상기 스크램블회로(32)는 한쪽 입력단에 상기 어드레스신호가 공급되고, 다른쪽 입력단에 상기 시큐리티 데이터가 공급되는 논리회로(32c)를 포함하고 있는 것을 특징으로 하는 시큐리티회로.4. The security circuit according to claim 3, wherein said scramble circuit (32) comprises a logic circuit (32c) supplied with said address signal to one input terminal and said security data supplied to the other input terminal. 제1항에 있어서, 상기 제1기억수단(1a)의 출력단에는, 이 제1기억수단(1a)으로부터 독출된 데이터 및 상기 시큐리티데이터가 공급되고, 상기 비교회로(6)로부터 불일치신호가 공급된 경우에 상기 시큐리티 데이터에 따라 상기 독출된 데이터를 변경시키는 데이터 변경회로(401∼40n)가 설치된 것을 특징으로 하는 시큐리티회로.The data read out from the first storage means 1a and the security data are supplied to an output terminal of the first storage means 1a, and a mismatch signal is supplied from the comparison circuit 6. And a data change circuit (40 1 to 40 n ) for changing the read data in accordance with the security data. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930022480A 1992-10-27 1993-10-27 Security circuit KR960006485B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP28856292 1992-10-27
JP92-288562 1992-10-27
JP93-251502 1993-10-07
JP5251502A JPH06208516A (en) 1992-10-27 1993-10-07 Security circuit

Publications (2)

Publication Number Publication Date
KR940009845A true KR940009845A (en) 1994-05-24
KR960006485B1 KR960006485B1 (en) 1996-05-16

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Application Number Title Priority Date Filing Date
KR1019930022480A KR960006485B1 (en) 1992-10-27 1993-10-27 Security circuit

Country Status (5)

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US (1) US5357467A (en)
EP (1) EP0595288A1 (en)
JP (1) JPH06208516A (en)
KR (1) KR960006485B1 (en)
CN (1) CN1034448C (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781627A (en) * 1994-08-03 1998-07-14 Fujitsu Limited Semiconductor integrated circuit device with copy-preventive function
JPH09293388A (en) * 1996-04-24 1997-11-11 Toshiba Corp Semiconductor storage device
DE19623145B4 (en) * 1996-06-10 2004-05-13 Robert Bosch Gmbh Method for operating a control device with a memory device programmable via a programming device
DE19708616C2 (en) * 1997-03-03 1999-09-02 Siemens Ag Electronic data processing equipment and system
AUPQ809600A0 (en) * 2000-06-09 2000-07-06 Mcom Solutions Inc Controller and memory for storing and processing security software and data
KR100837270B1 (en) * 2006-06-07 2008-06-11 삼성전자주식회사 Smart card and data security method thereof
JP5507513B2 (en) * 2011-09-12 2014-05-28 日立オートモティブシステムズ株式会社 Vehicle control device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5744299A (en) * 1980-08-26 1982-03-12 Mitsubishi Electric Corp Memory device
JPS5848298A (en) * 1981-09-14 1983-03-22 Nec Corp Information processor
JPS60177498A (en) * 1984-02-23 1985-09-11 Fujitsu Ltd Semiconductor storage device
US4757533A (en) * 1985-09-11 1988-07-12 Computer Security Corporation Security system for microcomputers
JPS6344242A (en) * 1986-08-11 1988-02-25 Fujitsu Ltd Microprocessor
US5081675A (en) * 1989-11-13 1992-01-14 Kitti Kittirutsunetorn System for protection of software in memory against unauthorized use
JPH03276345A (en) * 1990-03-27 1991-12-06 Toshiba Corp Microcontroller
JPH0476749A (en) * 1990-07-19 1992-03-11 Toshiba Corp Security circuit

Also Published As

Publication number Publication date
JPH06208516A (en) 1994-07-26
US5357467A (en) 1994-10-18
CN1086919A (en) 1994-05-18
KR960006485B1 (en) 1996-05-16
CN1034448C (en) 1997-04-02
EP0595288A1 (en) 1994-05-04

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