KR940009820A - 슈퍼 스칼라 컴퓨터 아키텍춰 및 그 운영 방법 - Google Patents
슈퍼 스칼라 컴퓨터 아키텍춰 및 그 운영 방법 Download PDFInfo
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- KR940009820A KR940009820A KR1019930020072A KR930020072A KR940009820A KR 940009820 A KR940009820 A KR 940009820A KR 1019930020072 A KR1019930020072 A KR 1019930020072A KR 930020072 A KR930020072 A KR 930020072A KR 940009820 A KR940009820 A KR 940009820A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
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Abstract
본 발명은 정확한 인터럽트, 재시작 및 분기 삭제에 의한 데이타 종속, 데이타 반종속 및 순차성의 보전을 관리하면서 비순서적인 명령어를 실행하기 위한 슈퍼 스칼라 컴퓨터 아키텍춰 및 그 운영 방법에 관한 것이다. 범용레지스터에 참조되는 소오스 및 종착지 어드레스를 리네임하고 재순환하는데 복수개의 레지스터와 표가 사용된다. 범용 레지스터에 있는 종착지 데이타에 대한 엑세스는 데이타와 연관된 명령어가 모두 실행될 때까지 록된다. 소오스 및 종착지 레지스터 모두를 리네이밍시키는 것에 의하여, 입력 명령의 순서와 동일하에 명령어 결과를 소거함으로써 순차성의 보전을 유지하면서 반종속성 문제를 피할 수 있다. 상기 시스템 및 방법은 복수개의 입력 명령과 복수개의 실행 유니트로 동작한다. 소오스 및 종착지 레지스터의 리네이밍에 의해 생성된 상기 제어워드는 초기의 명령과 크게 다르지 않으며, 상태와 시퀀스 정보를 프로세서 제어워드에 부가하는 것을 피할 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 아키텍춰에 있어서 레지스터와 실행 유니트의 바람직한 실시예에 대한 개략적인 블록도,
제3도는 제어워드의 형성을 묘사하는 기능도,
제4도는 본 발명에 따라 재순환하는 레지스터와 연관된 동작을 묘사하는 기능도.
Claims (13)
- 비순서적인 명령어를 실행하기 위한 슈퍼 스칼라 컴퓨터 아키텍춰에 있어서, 제어워드를 실행하기 위한 복수개의 실행 유니트 수단, 어드레스로 제어워드 데이타를 기억시키기 위한(for storing control word data by address)범용 레지스터, 범용 레지스터에 참조되는 리네임되어 재순환된 레지스터 어드레스(renamed and recycled register address referenced to the general purpose register)를 사용하여 이용가능한 실행 유니트 수단으로 전송하기 위한 제어워드를 형성하는 수단 및 실행 유니트 수단 내의 순서화된 제어워드의 실행에 응답하여 범용 레지스터의 어드레스를 재순환시키기 위한 수단을 구비하는 것을 특징으로 하는 슈퍼 스칼라 컴퓨터의 아기텍춰.
- 제1항에 있어서, 상기 범용 레지스터의 어드레스를 재순환시키는 수단은 순서에 있어서, 선행하는 제어워드가 실행되면(upon execution of control words which precede in order)레지스터 어드레스의 리네임을 갱신하는 것을 특징으로 하는 슈퍼 스칼라 컴퓨터 아키텍춰.
- 제1항에 있어서, 상기 범용 레지스터의 어드레스를 재순환시키는 수단을 훼치된 명령어(fetched instrctions)의 수와 일치하는 복수개의 보조표(multiple sub-tables)를 재순환시키는 것을 특징으로 하는 슈퍼 스칼라 컴퓨터 아키텍춰.
- 제2항에 있어서, 상기 제어워드의 형성 수단은 오피코드(opcode), 직접 리네임된 소오스 어드레스 및 충돌 벡터표로 리네임된 어드레스(collosion vector table renamed addresses)로 구성된 제어워드를 생성하는 것을 특징으로 하는 슈퍼 스칼라 컴퓨터 아키텍춰.
- 제3항에 있어서, 상기 제어워드의 형성 수단을 오피코드, 직접 리네임된 소오스 어드레스 및 충돌 벡터표로 리네임된 종착지 어드레스(collision vector table renamed destination addresses)로 구성된 제어워드를 생성하는 것을 특징으로 하는 슈퍼 스칼라 컴퓨터 아키텍춰.
- 입력 명령의 비순서적 실행을 허용하는 슈퍼 스칼라 아키텍춰 컴퓨터의 운영방법에 있어서, 하나의 리네임표(a first rename table)를 사용하여 복수개의 입력 명령의 소오스 레지스터 어드레스(source register address of multiple input instructions)를 리네임시키는 단계, 충돌 벡터표를 사용하여 복수개인 입력 명령의 종착지 레지스터 어드레스를 리네임시키는 단계, 이용가능한 실행 유니트를 사용하여 리네임된 소오스 레지스터 어드레스, 리네임된 종착지 레지스터 어드레스 및 충돌 벡터표 어드레스로 구성된 제어워드를 처리하는 단계 및 순서에 있어서, 선행하는 명령의 실행이 끝나면 어드레스를 재순환시키는 단계를 구비하는 것을 특징으로 하는 슈퍼 스칼라 아키텍춰 컴퓨터의 운영 방법.
- 제6항에 있어서, 상기 어드레스의 재순환 단계는 입력 명령의 순서에 대응하는 순서(in an order corresponding to the order of the input instructions)로 이루어지는 것을 특징으로 하는 슈퍼 스칼라 아키텍춰 컴퓨터의 운영 방법.
- 제7항에 있어서, 대응하는 실행 유니트에 의해 레지스터와 관련된 데이타가 생성될 때까지 종착지 레지스터에 있는 데이타에 대한 엑세스를 록킹(locking access to data in destination register)하는 단계를 더 구비하는 것을 특징으로 하는 슈퍼 스칼라 아키텍춰 컴퓨터의 운영방법.
- 제8항에 있어서, 레지스터와 관련된 데이타의 엔트리에 따라, 대응하는 종착지 레지스터에 대한 엑세스를 언록(unlocking access to the corresponding destination register)하고 충돌 벡터표의 대응하는 엔트리에 있는 종료 플래그를 세트(setting a finish flag)시키는 단계를 더 구비하는 것을 특징으로 하는 슈퍼 스칼라 아키텍춰 컴퓨터의 운영방법.
- 제9항에 있어서, 입력 순서로 명령이 완료되는 순서로 충돌 벡터표와 2번째 리네임 표(a second renamed table)사이의 어드레스를 재순환시키는 단계를 더 구비하는 것을 특징으로 하는 슈퍼 스칼라 아키텍춰 컴퓨터의 운영방법.
- 적어도 일부의 명령어가 아키텍춰된 레지스터에서 데이타에 대해 연산을 수행하는 순서환된 명령어 리스트(an ordered list of instructions)를 실행하기 위한 데이타 처리 장치에 있어서, 데이타를 기억하는 복수개의 범용 레지스터, 아키텍춰된 레지스터에 대응하며, 범용 레지스터의 어드레스를 포함하는 복수개의 리네임 레지스터, 각각의 명령어 대신에 제어워드를 제공하되, 각각의 제어워드는 자체 대응하는 리네임 레지스터 내에 포함된 범용 레지스터의 어드레스로서 특정하게 아키텍춰된 임의의 레지스터를 교체시키는 제어워드를 제공하기 위한 제어워드 수단, 상기 범용 레지스터에서 나오는 데이타상에 제어워드의 실행하기 위한 복수개의 실행 수단 및 제어워드의 실행 상태를 기억하기 위한 수단을 포함하며, 비순서적인 제어워드의 실행을 제공하면서 상기 범용 레지스터의 순서화된 명령어 데이타의 보전을 유지(maintaining ordered instruction data integrity)하는 각 실행 유니트의 제어워드 실행을 조정하기 위한 조정수단(regulation means for regulating execution of control words in each execution)을 구비하는 것을 특징으로 하는 데이타 처리 장치.
- 적어도 일부의 명령어가 아키텍춰된 레지스터에서 데이타에 대해 연산을 수행하는 순서화된 명령어 리스트(an ordered list of instruction)를 실행하기 위한 데이타처리장치에 있어서, 각각의 레지스터가 데이타를 수신할 수 있다는 것을 표시하는 수단을 포함하는 데이타를 기억하는 복수개의 범용 레지스터, 아키텍춰된 레지스터에 대응하며, 범용 레지스터의 어드레스를 포함하는 복수개의 리네임 레지스터, 각각의 명령어 대신에 각각의 제어워드를 제공하되, 각각의 제어워드가 자체 대응하는 리네임 레지스터 내에 포함된 범용 레지스터의 어드레스로서 특정하게 아키텍춰된 임의의 레지스터를 교체시키는 제어워드를 제공하기 위한 제어워드 수단, 상기 범용 레지스터에서 나오는 데이타상에 제어워드를 실행하기 위한 복수개의 실행수단 및 비순서적인 제어워드의 실행을 제공하면서, 상기 범용 레지스터의 순서화된 명령어 데이타의 보전을 유지하는 각 실행 유니트에서의 제어워드 실행을 조정하는 조정수단을 구비하는 것을 특징으로 하는 데이타 처리 장치.
- 제12항에 있어서, 상기 레지스터 표시수단은 레지스터가 데이타를 수신할 때까지 레지스터에 대한 엑세스를 록하는 수단을 포함하는 것을 특징으로 하는 데이타 처리 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US96969592A | 1992-10-30 | 1992-10-30 | |
US07/969,695 | 1992-10-30 |
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KR940009820A true KR940009820A (ko) | 1994-05-24 |
KR970004509B1 KR970004509B1 (ko) | 1997-03-28 |
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KR1019930020072A KR970004509B1 (ko) | 1992-10-30 | 1993-09-28 | 슈퍼 스칼라 컴퓨터 아키텍춰 및 그 운영 방법 |
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US (1) | US5481683A (ko) |
EP (1) | EP0600611B1 (ko) |
JP (1) | JP2698033B2 (ko) |
KR (1) | KR970004509B1 (ko) |
CN (1) | CN1053508C (ko) |
AT (1) | ATE189071T1 (ko) |
CA (1) | CA2098414C (ko) |
DE (1) | DE69327637T2 (ko) |
TW (1) | TW306987B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100343601B1 (ko) * | 1998-02-17 | 2002-07-11 | 포만 제프리 엘 | 무순서 레지스터 동작용 장치를 구비하는 데이터 처리 시스템 및그 방법 |
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Publication number | Priority date | Publication date | Assignee | Title |
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1993
- 1993-03-19 US US08/034,193 patent/US5481683A/en not_active Expired - Fee Related
- 1993-06-15 CA CA002098414A patent/CA2098414C/en not_active Expired - Fee Related
- 1993-09-08 TW TW082107359A patent/TW306987B/zh not_active IP Right Cessation
- 1993-09-28 KR KR1019930020072A patent/KR970004509B1/ko not_active IP Right Cessation
- 1993-10-25 JP JP5265946A patent/JP2698033B2/ja not_active Expired - Fee Related
- 1993-10-28 CN CN93119608A patent/CN1053508C/zh not_active Expired - Fee Related
- 1993-11-01 AT AT93308705T patent/ATE189071T1/de not_active IP Right Cessation
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KR100343601B1 (ko) * | 1998-02-17 | 2002-07-11 | 포만 제프리 엘 | 무순서 레지스터 동작용 장치를 구비하는 데이터 처리 시스템 및그 방법 |
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CA2098414C (en) | 1997-05-13 |
EP0600611A2 (en) | 1994-06-08 |
US5481683A (en) | 1996-01-02 |
EP0600611A3 (en) | 1995-01-11 |
ATE189071T1 (de) | 2000-02-15 |
TW306987B (ko) | 1997-06-01 |
CN1053508C (zh) | 2000-06-14 |
DE69327637T2 (de) | 2000-07-06 |
DE69327637D1 (de) | 2000-02-24 |
CA2098414A1 (en) | 1994-05-01 |
CN1105138A (zh) | 1995-07-12 |
JPH06214784A (ja) | 1994-08-05 |
JP2698033B2 (ja) | 1998-01-19 |
EP0600611B1 (en) | 2000-01-19 |
KR970004509B1 (ko) | 1997-03-28 |
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