KR940009577B1 - Isolation method of semiconductor device - Google Patents

Abstract

The isolation method includes the steps of sequentially forming first and second insulating layers on a semiconductor substrate, etching the second insulating layer to form a contact hole, removing a predetermined portion of the first insulating layer to expose a portion of the substrate, forming an oxide layer on the exposed portion of the substrate, forming a spacer on the inner wall of the contact hole, forming a first field oxide layer on the exposed portion of the substrate on which the spacer is not formed, ion-implanting impurities into the first field oxide layer, forming a second field oxide layer on the overall surface of the first field oxide layer, and removing the first and second insulating layer, and oxide layer, thereby preventing the impurities from penetrating into an active region.

Description

Device Separation Method of Semiconductor Device

1A to 1D are process flow charts illustrating an element separation process of a semiconductor device by a conventional method.

2A to 2C are process flowcharts illustrating a device isolation manufacturing process of a semiconductor device by another conventional method.

3A to 3F are process flow charts illustrating a device isolation manufacturing process of a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a device isolation method for a semiconductor device.

Recently, with the development of semiconductor device manufacturing technology and the application of memory devices, the development of large-capacity semiconductor devices is progressing, and the increase in the capacity of these semiconductor devices is based on the microprocessing technology that is doubled for each generation. It has been promoted by memory cell research. The reduction of device isolation regions between patent devices is one of the important items in the description of memory devices.

As the device isolation technology, LOCOS (LOCal Oxidation of Silicon) technology, which selectively grows a thick oxide film on a semiconductor substrate and uses it as a separation region, has been mainly used until recently.

1A to 1D are process flow charts illustrating a device isolation method of a conventional semiconductor device using the LDCOS method, in which a buffer oxide film 12 and a non-oxidizing nitride film 14 are sequentially formed on a semiconductor substrate 10. After forming (FIG. 1a), the photolithography mask pattern 16 is formed, wherein the photolithography mask pattern is formed by exposing a buffer oxide film of a portion to form a field oxide film. Subsequently, the exposed nitride layer is removed by applying a mask pattern to form an opening 9, and an impurity ion of a conductive type such as the semiconductor substrate 10 is implanted to inject the channel blocking layer 18. To form. For example, when the semiconductor substrate 10 is doped with p-type impurities, the impurity ions may use boron (B ⁺ ) ions or other trivalent ions (FIG. 1b). The field oxide film 20 is formed by removing the photolithography mask pattern and then exposing the semiconductor substrate 10 to a high temperature wet oxidation process. In this case, the nitride film having the opening 9 formed therein may be a semiconductor material. Since it serves to protect the substrate, the field oxide film is formed only in the region where the surface is exposed by the opening 9.

2H ₂ O + Si-→ SiO ₂ + 2H ₂ ^. … … … … … … … … … … … … … … … … (One)

When the water vapor (H ₂ O) is supplied to the semiconductor substrate, oxygen ions constituting the water vapor and silicon ions constituting the semiconductor substrate are combined to form silicon dioxide (SiO ₂ ). Since it is formed by the same principle, silicon ions consumed to bond with oxygen ions are formed in the form of erosion on the surface of the semiconductor substrate of the principle. Usually, the erosion degree corresponds to about 0.44 times the thickness of the field oxide film on the lower surface of the substrate, and the thickness and length of the field oxide film are substantially the same on the side surface. The side erosion of the field oxide film is referred to as bird's beak, which makes it difficult to form a pattern by eroding the device formation region. In a semiconductor device in which the size of the device formation region is smaller than that of the Buzzbeek The problem is serious (Figure 1c). Subsequently, the nitride film and the buffer oxide film are sequentially removed to complete the field oxide film 20 for device isolation (FIG. 1D). 1B to 1D, it can be seen that the size of the active region (FIG. 1B) expected before the oxidation process is much smaller after the oxidation process (FIG. 1D).

2A to 2C are process flow charts illustrating a device isolation method of a semiconductor device according to another method, which has been proposed to prevent erosion of a device formation region due to Buzzbee.

After the pad oxide film 11 and the non-oxidizing nitride film 15 are sequentially stacked on the semiconductor substrate 100, a photoetch mask pattern is formed, and the mask pattern is applied to the nitride film 15 and the pad oxide film by RIE. The opening 11 is formed by etching 11 (FIG. 2A).

The field oxide film 19 is formed by removing the photolithography mask pattern and then exposing the semiconductor substrate 100 to a high temperature wet oxidation process. In this case, the nitride film in which the opening 17 is formed may be a semiconductor material for the oxidation process. Since the substrate serves to protect the substrate, the field oxide film 19 is formed only in the region where the surface is exposed by the opening 17 (FIG. 2B). In this case, it is possible to prevent the erosion of the device active region due to the buzz beak according to the thickness of the buffer nitride film and the thickness of the pad oxide film. If the device isolation design dimension is 0.4 μm, the nitride film should be formed at 1500Å and the pad oxide film at 160Å. . However, in this case, erosion of the device formation region due to the buzz bee can be prevented, but since the pit of the boundary between the device isolation region and the device formation region is pitted and an electric field is concentrated on the portion of the gate oxide film, Electrical characteristics are degraded. In addition, in order to prevent the Burj beak, a non-oxidizing material SiON (nitroso silicon) is used instead of the pad oxide film, but the same phenomenon occurs at this time. Subsequently, after the field oxide film 19 is formed, the buffer nitride film and the pad oxide film are removed by treatment with BOE (Buffered Oxide Etchant) (FIG. 2C).

Accordingly, an object of the present invention is to provide a device isolation fabrication method of a semiconductor device capable of minimizing device isolation regions and improving electrical characteristics of the device by forming a buzz beak of a suitable size in order to solve the above problems. To provide.

In order to achieve the above object, the device isolation fabrication method of the present invention includes the steps of sequentially layering a first insulating film and a second insulating film on the entire surface of the semiconductor substrate, and forming an opening by etching the second insulating film; Exposing a portion of the semiconductor substrate by removing a predetermined portion of the first insulating film; Forming an oxide film on the exposed portion of the semiconductor substrate to control the biz; Forming a spacer on an inner wall of the opening; Growing a first field oxide film through an exposed portion of the semiconductor substrate on which the spacer is not formed; Implanting impurity ions through the first field oxide film; Forming a second field oxide film over the first field oxide film; And removing the oxide film for adjusting the first insulating film, the second insulating film, and the burj beak.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3A to 3G are process flowcharts illustrating a device isolation fabrication process of a semiconductor device according to the present invention.

First, referring to FIG. 3A, a material for forming a first insulating film 11 on the semiconductor substrate 100 to a thickness of about 300 GPa and forming a second insulating film on the first insulating film 11 may be, for example. Silicon nitride (SixNy) is deposited to a thickness of at least 1500 GPa to form a second insulating film 15. Subsequently, a photolithography mask pattern is formed on the second insulating film 15, and the mask pattern is applied to form an opening 18 for defining an inactive region by etching the second insulating film 15. Remove it.

Referring to FIG. 3B, a predetermined portion of the first insulating layer 11 is wet-etched and removed by a BOE (Buffered Oxide Etchant) solution or a HF (Hydrogen Fluoride) solution through the opening 18. A portion of the semiconductor substrate is exposed, and an oxide film 17 having a thickness of about 100 μs is formed to control the size of the Buzz beak by a thermal oxidation method through the exposed portion of the semiconductor substrate.

Referring to FIG. 3C, for example, a nitride film is formed to a thickness of about 1500 kPa as a third insulating film on the entire surface of the resultant after the process of forming the buzz bead adjustment oxide film 17, and the nitride film and the buzz bead adjustment oxide film 17 and A portion of the upper portion of the semiconductor substrate is formed by the spacer 19 by anisotropic etching at once, and part of the semiconductor substrate is overetched and exposed. In this case, the thickness ratio of the nitride film forming the spacer 19 and the buzz bead adjusting oxide film 17 should be 15: 1 or more.

Referring to FIG. 3D, the first field oxide film 21 is grown to a thickness of about 1000 to 3000 mW through the semiconductor substrate exposed in the spacer 19 forming process, and then the impurity ions are formed through the first field oxide film 21. Is injected to form the channel blocking layer 23. At this time, the thickness of the first field oxide film 21 grown is [pad oxide film thickness + SiN]. As a result, impurity ions do not enter the active region at the time of ion implantation, and enter the semiconductor substrate under the first field oxide film.

Referring to FIG. 3E, a second field oxide film having a thickness of about 1000 mV is grown by the thermal oxidation method through the first field oxide film 21 to form a field oxide film 25 including the first and second field oxide films. do. Thus, the thickness of the bead beak is formed to about 600Å.

Referring to FIG. 3F, the spacer and the second insulating film are treated with a phosphoric acid solution and removed, and the first insulating film is treated with a BOE solution or an HF solution and removed. At this time, the Buzz bead adjustment oxide film is also removed, the portion is slightly lower.

The semiconductor device according to the present invention by the above process is limited to form a buzz bead control oxide film of about 100Å thickness and removed after the formation of the field oxide film, it is possible to prevent the formation of excessive buzz beak on the side when growing the field oxide film, Such an appropriate amount of Buzzbee can maintain the electrical characteristics of the device by preventing the dent of the interface between the device formation region and the device isolation region.

In addition, since the impurity ions for channel blocking are implanted after the formation of the first field oxide film and the second field oxide film is formed again, impurities into the active region that may occur when impurity ions for channel blocking are implanted after growing the field oxide film at once. Since the penetration can be prevented, the breakdown voltage characteristic is improved.

Claims (8)

Sequentially laminating a first insulating film and a second insulating film on the entire surface of the semiconductor substrate; Etching the second insulating film to form an opening; Exposing a portion of the semiconductor substrate by removing a predetermined portion of the first insulating film; Forming an oxide film on the exposed portion of the semiconductor substrate for adjusting the burj beak; Forming a spacer on an inner wall of the opening; Forming a second field oxide film through an exposed portion of the semiconductor substrate on which the spacer is not formed; Implanting impurity ions through the first field oxide film; Forming a second field oxide film over the first field oxide film; And removing the first insulating film, the second insulating film, and the oxide film for adjusting the burj beak. 2. The method of claim 1, wherein the oxide film for adjusting the burj beak comprises a step of forming a thickness of about 100 microseconds by a thermal oxidation method through an exposed portion of the semiconductor substrate. . 2. The method of claim 1, wherein the second insulating film forms a nitride film having a thickness of about 1500 GPa. The method of claim 1, wherein the spacer is formed after the oxide film forming process for adjusting the buzz beak to form a third insulating film on the entire surface of more than 1500Å, anisotropically etching the third insulating film and the Buzz beak control oxide film And over-etching a predetermined portion of the upper portion of the semiconductor substrate. 5. The method of claim 4, wherein the third insulating film is a nitride film. The method of claim 1, wherein the first field oxide film has a thickness of a pad oxide film + a thickness of a buffer nitride film x A device isolation method for a semiconductor device, comprising the step of forming lower. 2. The method of claim 1, wherein the thickness ratio of the spacer on the inner wall of the opening to the oxide film for adjusting the buzz beak is 15: 1 or more. 2. The method of claim 1, wherein the sidewall size of the burj beak is about 600 mu m when the thickness of the oxide film for adjusting the burj beak is 100 mu m and the thickness of the spacer is 1500 mu m.