KR940008483B1 - Interrupt controller - Google Patents

Abstract

The invention is an interrupt controller of which an interrupt input recognizes both falling edges and rising edges. The controller comprises edge detectors recognizing rising edges and falling edges of interrupt inputs; interrupt mask latches for disabling or enabling edge detectors; priority decoder and interrupt vector generation logic; a latch holding the most significant bits of vector. The edge detector comprises two flip-flops (31,32) detecting falling edges and rising edges of the interrupt request input; AND gates (34,35) clearing the edge detectors by logical-ANDing clear signal from priority decoder and vector generating logic with enable values of interrupt mask latches.

Description

Interrupt controller

1 is a block diagram of an embodiment of an interrupt controller according to the present invention.

FIG. 2 is a circuit diagram of an embodiment of the edge detector of FIG.

3 is a circuit diagram illustrating an example of a priority decoder and a vector generator in FIG.

4 is a schematic request block diagram of an electronic switching system to which the present invention is applied.

* Explanation of symbols for the main parts of the drawings

1, 2 latch portion 3, edge detection portion

4: priority decoder and vector generator 5: vector latch

The present invention relates to an interrupt controller. In particular, the device control processor system receives an interrupt request input from various interrupt sources and requests an interrupt from the processor, and generates an interrupt vector corresponding to the priority of the request input when the processor receives an interrupt response signal. An interrupt controller.

Conventional interrupt controllers generate interrupts only when the interrupt request signal is active. Therefore, the interrupt controller generates an interrupt every time a signal value changes (transition: from 0 to 1 or 1 to 0). In this case, whenever the signal changes through the additional device, it must be converted into a signal that the interrupt controller can recognize as an interrupt.

As an example, an interrupt controller, such as Intel's 8259A, requests an interrupt from the processor when the input reaches a logic value of 1, and must remain at logic value 1 until an interrupt acknowledgment is received from the processor. The level triggering method is adopted.

However, in the case of using such an interrupt controller, in order to generate an interrupt every time a signal is converted, a device for maintaining a logic value 1 for a predetermined time every time the input signal is changed must be added.

On the other hand, edge-triggered interrupt controllers, such as Motorola's MC68901, are designed to either generate an interrupt when the signal changes or select one of the polling and rising edges by a register.

Therefore, if you want to generate an interrupt every time the signal changes, connect the signal to two inputs, one input polling edge and the other input to generate an interrupt on the rising edge. have.

However, in the processor, interrupts generated from polling edges and interrupts generated from rising edges are recognized as separate interrupts, and because their priority is different, they must be processed separately so that they are recognized as the same interrupt by software. In order to do this, there is a problem that two inputs must be used.

Accordingly, the present invention has been made to solve the above problems, by combining a circuit that generates an interrupt by the falling edge and the rising edge at one input, and the falling edge, rising edge, or falling edge with the operation of the register. Interrupts can be generated by all of the rising edges, and a combination of a number of these devices has a priority to request an interrupt to the processor according to the priority when the interrupt occurs, and generate an interrupt vector to distinguish the interrupts. Its purpose is to provide an interrupt controller.

In order to achieve the above object, the present invention provides an interrupt controller which receives an interrupt request input from an interrupt generation source, requests an interrupt from the processor, and generates an interrupt vector corresponding to the priority of the request input when receiving an interrupt response signal from the processor. Edge detection means for detecting a rising edge and a falling edge by receiving a plurality of interrupt request inputs having priority; First latch means for inputting and storing a value for enabling or disabling the polling edge detection operation of the edge detection means connected to the output terminal; Second latch means for inputting and storing a value for enabling or disabling the rising edge detection operation of the edge detection means connected to the output terminal; Receives the output of the edge detection means and requests an interrupt. When receiving the interrupt response, outputs an interrupt vector corresponding to the priority value of the highest priority among the signals input from the edge detection means, and sends the priority element to the edge detection means. Priority decoder and vector generating means for outputting a signal for clearing; And a third latch means for storing the vector value of the higher bit to form a complete interrupt vector in combination with the vector output from the priority decoder and the vector generating means, for the rising edge, the falling edge, or both of the interrupt request input. Enables selective interrupt generation at the edge.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of an embodiment of an interrupt controller according to the present invention. Although the interrupt controller of the present invention has no limit on the number of inputs, the present invention shows an example of a configuration having eight inputs.

In the drawings, 1 and 2 denote latch portions, 3 denote edge detection portions, 4 denote priority priorities and vector generators, and 5 denote vector latches.

As shown in the figure, the interrupt controller of the present invention includes a processor for detecting an edge of an interrupt request input signal and a processor when one or more signals among eight signals inputted from the edge detector 3 are activated. Priority decoder that generates an interrupt vector of 3 bits corresponding to the highest priority value among the active input signals and outputs a signal to clear the edge detection part of the priority when an interrupt is requested from the processor and an interrupt response is received from the processor. And a 5-bit vector for storing the vector generator 4 and the higher vector designated by the processor and simultaneously outputting the 3-bit vector generated by the vector generator in response to an interrupt to give the 1-byte vector to the processor. Falling edge detection and rising edge detection motion of the latch unit 5 and the signal input to the edge detection unit 3, respectively Further comprises two 8-bit latch section (1, 2) for determining whether to perform.

In addition, the present invention combines two edge detection elements for detecting edges and rising edges in order to detect edges in the input signal, and inputs the detection elements with the highest priority through a plurality of priority encoders. It requests an interrupt from the processor and generates an interrupt vector at the same time. When the processor receives an interrupt response, it supplies the processor with the highest priority vector and clears the edge detector with that priority.

The edge detector 3 may enable or disable the falling edge detector and the rising edge detector, respectively, by means of a control register. When the edge detector 3 is disabled, interrupts are not generated. If only the enable is enabled, an interrupt is generated by the falling edge. If only the rising edge detection element is enabled, an interrupt is generated by the rising edge. When all are enabled, an interrupt is generated whenever the input signal changes.

The edge detector 3 detects a rising edge and a falling edge by receiving a plurality of interrupt request inputs having priority.

The latch unit 1 has an input terminal coupled to the data bus and an output terminal coupled to the polling edge enable terminal of the edge detector 3, respectively, and enables or disables the polling edge detection operation of the edge detector 3. Is to store the value to

The latch unit 2 has an input terminal coupled to the data bus and an output terminal coupled to the falling edge enable terminal of the edge detector 3, respectively, and enables or disables the rising edge detection operation of the edge detector 3. Save the value

The priority decoder and the vector generator 4 are connected between the edge detector 3 and the processor. When one or more of the eight signals input from the edge detector 3 are activated, an interrupt is requested from the processor. When an interrupt response is received from the processor, a three-bit interrupt vector corresponding to a priority value of the highest priority among the active input signals is generated, and a signal for clearing the detection element in the edge detection unit 3 of the corresponding priority is cleared. Output

The vector latch unit 5 is connected to a data bus, the priority decoder and the vector generator 4, and stores a higher vector stored by a processor, and the priority decoder and the vector generator 4 in response to an interrupt response. It is a 5-bit latch that stores the vector value of the high-order bit to form a complete interrupt vector of 1 byte and combines it with the 3-bit vector generated by the.

2 is a circuit diagram of an edge detector according to an exemplary embodiment of the present invention, and is for one input.

Therefore, in the case of having eight inputs as shown in FIG. 1, eight such edge detector circuits are required.

As shown in the figure, the edge detector includes a flip-flop 32 for detecting a rising edge from one interrupt request input signal, an inverter 33 connected to the interrupt request input terminal and inverting the input signal, and an inverted input. A flip-flop 31 for receiving polling edges, an AND gate 36 for making the sub-outputs of the two flip-flops 31 and 32 into one output, and the transfer of the interrupts to complete the priority decoder and the vector. AND gates 34 and 35 for receiving a clear signal from the generator 4 and a falling edge enable or rising edge enable signal to logically multiply to clear the flip-flop of the edge detector 3, and the AND gate 36. ), An input is connected to an output terminal, a clear signal output terminal of the priority decoder and the vector generator 4, and an OR gate 37 connected to the two AND gates 34 and 35, respectively.

The two AND gates 34 and 35 connected to the clear terminals of the flip-flops 31 and 32 are connected to signals (falling edge enable and rising edge enable) to determine whether the flip-flop is operated. Detection of edges can be selectively controlled.

3 is a circuit diagram of an embodiment of the priority decoder and the vector generator 4 according to the present invention, which receives the output of the edge detector 3 and requests an interrupt from the processor, and has the highest priority when an interrupt response signal is received from the processor. A circuit for outputting an interrupt vector and generating a signal for clearing the flip-flop in the edge detector of the priority.

As shown in the figure, the priority and decoder and vector generator 4 includes an AND gate 41 which generates an interrupt request signal when one or more signals among a plurality of signals input from the edge detector 3 are activated. The priority encoder 42 outputs the priority value of the highest priority signal among the active input signals as a combination of binary signals, and receives the interrupt response signal from the processor. 3-bit latch 43 for latching the output of the encoder and outputting the latched value as part of the vector, and when the value stored in the latch 43 is outputted, the output is received and the interrupt of the priority is transmitted to the edge detector 3. It is composed of a decoder 44 such as TTL74138 as generating a clear signal indicating that this is completed.

The output of the latch 43 becomes part of the interrupt vector value input to the processor, which generates the edge detector clear signal of the corresponding priority through the decoder 44, so that even if multiple inputs are applied simultaneously, the highest priority It is processed in turn from the input.

FIG. 3 is an example of eight interrupt inputs from the edge detector. If the number of inputs is different, the priority encoder 42 and the decoder 44 process the corresponding number, and the latch 43 You can also adjust the number of bits to fit the input number.

Then, an interrupt output (INTREQ) signal is generated whenever one or more active signals among the plurality of inputs having the priority received from the edge detector 3 are generated, and when the interrupt response signal is received, the signals are activated from the plurality of input signals. Among these, the priority of the highest priority signal is output as a binary value and a clear signal of the corresponding priority is generated.

4 is an example in which the present invention is applied to TDX-10 (registered trademark) electronic exchange, which is a domestic electronic exchanger.

That is, two subprocessors (A, B) are redundant, and one subprocessor has control of the device (C). The device control right is determined by the control bus select signal output from the two subprocessors (hereinafter referred to as TBSEL). TBSEL (A) output from subprocessor A and TBSEL (B) output from subprocessor B have the same value. If it has, subprocessor B has control of the device, and if it has a different value, processor A has control of the device.

Therefore, each subprocessor knows whether it has its own control right by receiving the other's TBSEL signal and compares it with its own TBSEL, and can also change its TBSEL to bring its own control right.

As such, the two subprocessors can change the control right by changing the TBSEL at any time, so that the sub-processor must detect the change in the TBSEL of the other side and respond appropriately to the change in the control right. In this case, when the subprocessor inputs the counterpart TBSEL signal to the interrupt controller of the present invention, the subprocessor generates an interrupt whenever the counterpart TBSEL signal changes, so that the subprocessor can quickly detect a change in the counterpart TBSEL signal.

Accordingly, the interrupt controller of the present invention as described above can selectively generate interrupts at the falling edge, rising edge, or both of the input signals according to the values of the latches 1, 2, so that the active value of the input signal is zero. Alternatively, regardless of 1), an interrupt can be generated, and an interrupt can be generated whenever an input signal is changed, so that various interrupt sources can be connected and used without going through a separate process.

Claims (4)

An interrupt controller that receives an interrupt request input from an interrupt source and requests an interrupt from a processor, and generates an interrupt vector corresponding to a priority of a request input when an interrupt response signal is received from the processor. Edge detection means for detecting the rising edge and the falling edge (3): First latch means (1) for inputting and storing a value for enabling or disabling the polling edge detection operation of the edge detection means (3) connected to the output terminal ): Second latch means (2) for inputting and storing a value for enabling or disabling the rising edge detection operation of the edge detection means (3) connected to the output terminal; Receives the output of the edge detection means 3, requests an interrupt, and receives an interrupt response, outputs an interrupt vector corresponding to a priority value of the highest priority among the signals input from the edge detection means 3, and outputs the edge detection. Priority decoder and vector generating means (4) for outputting a signal for clearing the element of the corresponding priority to the means (3); And a third latch means (5) for storing the vector value of the higher bit so as to form a complete interrupt vector in combination with the vector output from the priority decoder and the vector generating means (4). An interrupt controller capable of selectively generating an interrupt at the falling edge or at both edges. 2. The apparatus as claimed in claim 1, wherein said edge detecting means (3) comprises: a first flip-flop (31) for detecting a falling edge with respect to one interrupt request input; A second flip-flop (32) for receiving a reversed input for the one interrupt request input and detecting a rising edge; A first AND gate 36 which multiplies and outputs outputs of the first and second flip-flops 31 and 32; And second and third AND gates for performing an AND operation on the clear signal input from the priority decoder and the vector generating means 4 and the falling edge enable or rising edge enable input to clear the first and second flip-flops. 34, 35, characterized in that the interrupt controller. 3. The edge detecting means (3) according to claim 2, wherein the edge detecting means (3) logically combines the output of the first AND gate and the clear signal output of the priority decoder and the vector generating means (4) to the input terminals of the second and third AND gates. And an OR gate (37). The fourth AND gate (4) according to any one of claims 1 to 3, wherein the priority decoder and the vector generating means (4) logically multiply all of a plurality of input signals having a priority input from the edge detecting means (3). 41); A priority encoder 42 for outputting the priority of the highest priority signal activated among the plurality of input signals having the priority in binary combination; A third latch 43 which latches the value output from the priority encoder upon receiving the interrupt response signal and outputs the latched value as part of the vector; And a decoder (44) for receiving a latch (43) output composed of a binary combination and clearing a signal line corresponding to the value upon receiving an interrupt response signal.