KR940008477B1 - Microcomputer interface unit - Google Patents

Abstract

The interface device translates a serial data (SDI) transmitted from a micom to a parallel data to control a digital server IC, decode the translated data, and load the data into an instruction register. The device comprises a serial-to-parallel converter (7), a latch (8) containing the translated one byte parallel data, a multiplexer (9) and a decoder (10), a NOR gate (11) to output a latch clock (/1CMD(n)) of the register, a D flip-flop (12) to synchronize a strobe signal (/STB) to a main clock (CLK), a delay unit (13), a latch (14), a decoder (15), a unit (16) to delay an output enable signal (/2BE) of the decoder (10) with 1 strobe cycle, a NOR gate (17) to output a latch clock (/2CMD(m)) of the register, an encoder (18), a multiplexer (19) to output a sense signal (SENSE).

Description

Micom interface device of digital servo IC

Block diagram of the digital servo IC shown in FIG.

(A), (b) and (c) of FIG. 2 are schematic signal timing diagrams of a microcomputer interface.

3 is a circuit diagram of a microcomputer interface device of the present invention.

(A) to (k) of FIG. 4 are signal timing diagrams of respective portions of the circuit of FIG.

(A) of FIG. 5 is a one byte instruction format, and (b) is a two byte instruction format.

* Explanation of symbols for main parts of the drawings

7: Serial / parallel converter 8,14: Latch

9,19: multiplex 10,15: decoder

11,17: NOR gate 12: D flip-flop

13: delay unit 18: encoder

The present invention relates to an interface device between a digital servo IC and a microcomputer applied to a reproducing system of a compact disc player and a laser disc player. In particular, the serial data output from the microcomputer is input to convert the parallel servo data into parallel data to control the digital servo device. And a microcomputer interface device of a digital servo IC which decodes the converted data and supplies the decoded data to a corresponding command register.

The analog servo IC provided as a conventional servo IC and a microcomputer interface device decode a command from a microcomputer and input a sequencer to output a control signal to control a switch inside the analog servo chip. The interface device has a limitation that the microcomputer cannot input data to the servo IC, and therefore, an interface device with the digital servo IC and a digital servo IC must be provided to overcome this problem.

In other words, the analog servo device performs the desired servo control by adjusting the resistance (R) and condenser (C) values outside the servo chip when adjusting any value. However, in the digital servo device, the desired control target value is adjusted based on the data from the microcomputer. An interface device with a microcomputer is required.

The present invention performs serial / parallel conversion, generalization of multiplexers and latches, and data decoding through a decoder in synchronization with the main clock. Therefore, digital servo control is performed by supplying instruction data corresponding to each register. The purpose of the present invention is to provide a microcomputer interface device of a digital servo IC, which will be described below. Referring to FIG.

That is, the digital servo IC includes an interface device (1) in charge of data interfacing with the microcomputer, a tracking counter (2) which counts the number of tracks to be traversed during a jump when controlling a compact disc or a laser disk, and an A / D. The mirror detector 3 which provides an envelope of the RF signal to the tracking counter 2 among the time-divided output signals of the converter 4, the tracking error signal TE (TE1), the focus error signal FE, and the tilt error signal. (TILT), an A / D converter (4) for time-dividing an RF signal and outputting the digital signal to the mirror detector (3) and the data bus (DATA BUS), a loop filter, an automatic sequencer, etc. After processing the output data of 4), the processing unit 5 to supply the PWM converter 6 and output the pulse width modulation (PWM) signal as the control information by the control target according to the output data of the processing unit 5 Consists of a PWM converter (6) and each circuit has a CONTROL BUS It is controlled through.

In such a digital servo IC, the microcomputer interface device 1 receives serial data / command information (SDI) for transmitting data and commands as shown in (a) of FIG. 2, and every time one bit of serial data is input as shown in (b). As shown in the supplied serial data clock (SDCLK) and (c), the strobe signal (/ STB) is supplied every 1 byte (8 bits), and the data is latched at the rising edge of the serial data clock (SDCLK). At the falling edge of the strobe signal (/ STB), one byte of data is latched, and a command from the microcomputer is decoded to provide data to the processing unit 5, and to each command of the digital servo IC. It outputs a signal SENSE indicating the status information (STAT).

In this way, the interface between the microcomputer and the digital servo IC is performed. As shown in FIG. 3, the interface device receives serial data / command information (SDI) and a clock (SDCLK) from the microcomputer as shown in FIG. / Parallel converter 7 for converting the data into parallel data, a latch 8 for storing parallel 1-byte information, a multiplexer 9 for selectively outputting the upper 4 bits of the output of the latch 8, and a multiplexer ( 9) Outputs a latch clock (/ 1CMD (n)) of a register by logically combining a decoder 10 that decodes a 1-byte or 2-byte instruction, and the output of the decoder 10 and a delayed strobe signal (/ DSTB). A NOR gate 11, a D flip-flop 12 for outputting the strobe signal / STB in synchronization with the main clock CLK, a delay unit 13 for delaying the synchronized strobe signal / STB, and To store the output lower 4 bit data of the latch (8). Value 14, a decoder 15 for decoding the latch 14 output according to the delayed 2-byte enable signal (/ D2BE), and an output 2-byte enable signal (/ 2BE) of the decoder 10. The delay unit 16 delays with a strobe period, and a latch clock (/ 2CMD) of the register by logically combining the output data of the decoder 15 according to the delayed strobe signal (/ DSTB) and the delayed 2-byte enable signal (/ D2BE). (m)), an NOR gate 17 for outputting, an encoder 18 for encoding a latch clock (/ 1CMD (n), / 2CMD (m)) and a 2-byte enable signal (2BE), and 3 to 5 are constituted by a multiplexer 19 which outputs a sense signal SENSE by combining the state information STAT from the processing unit 5 of the digital servo IC under the control of the encoder 18 output. Referring to the microcomputer interface operation according to the present invention with reference to as follows.

First, in FIG. 3, the reset signal / RESET normally sets the D flip-flop 12 and the delay parts 13 and 16, so that each output Q is all high (= 1). have.

Therefore, the output Q of the delay unit 16 (= / D2BE) becomes high and this high signal is supplied to the selection control stage S of the multiplexer 9, so that the multiplexer 9 is connected to the input stage I1 and the output stage. (0) is switched on, and the reset signal / RESET is inputted to the clear terminal / CLR of the latch 8 so that the latch 8 is cleared (Q = 0).

In this way, serial data / command information (SDI) is input from the microcomputer to the serial / parallel converter 7 in 1 or 2 bytes, and this data is 1 byte (8 bits) of parallel data by the serial data clock (SDCLK). Is converted to and outputted (see (a) and (b) in FIG. 4).

In this case, the instruction format is composed of one byte as shown in (a) of FIG. 5 or two bytes as shown in (b), and the one-byte instruction is composed of four bits of instruction and four bits of data, and the instruction is made of data other than (0111). to be. In the two-byte command, one byte consists of 0111 and the command, and the second byte consists of data.

As described above, the parallel data output from the serial / parallel converter 7 is stored in the latch 8, where the strobe signal / STB is output from the D flip-flop 12 in synchronization with the main clock CLK. The inverting strobe signal STB 'outputted from the inverting output terminal / Q is supplied to the clock of the latch 8 to interfere with the data latch 8 (see (c) and (d) of FIG. 4).

The output data of the latch 8 is supplied to the input terminal I1 of the multiplexer 9 and the multiplexer 9 outputs the data of the input terminal I1 to the output terminal 0, so that the output data is the decoder 10. Is decoded by

First, in the case of the one-byte instruction, as the one-byte instruction is input to the input terminal I of the decoder 10, as the decoding result, the n-th one-byte instruction signal (/) as shown in FIG. 1BC) is activated and this signal is input to the other side of the NOR gate 11.

On the other hand, the strobe signal (/ STB) output from the D flip-flop 12 is applied to the delay unit 13 and is output by being delayed by one clock in synchronization with the main clock CLK. (H) of FIG. 4 is input to the other side of the NOR gate 11.

Therefore, the nth NOR gate 11 (NOR gate is configured as the number of outputs of / 1BC (n = 15) and / 1BC is input respectively, / DSTB is common input) is specified in the decoded command (/ 1BC). Active to high, the latch clock (/ 1CMD (n)) of the register is output as shown in FIG.

At this time, the output data of the latch 8 supplies the lower 4 bits of the output MIFB-D to the command register and the latch pulse (ie, / 1CMD (n)) to the corresponding register.

On the other hand, when a 2-byte instruction is input ((a) in FIG. 3, 2BT-C), since the upper four bits of the first byte of the decoding result in the decoder 10 are 0111 (see (b) in FIG. 5), 2 bytes Only the enable signal / 2BE becomes low (= 0) as shown in (f) of FIG.

Therefore, since the input terminal D of the delay unit 16 goes low, when the strobe signal / STB is applied as a clock, the signal of the output terminal Q becomes a 2-byte enable signal / D2BE delayed by one strobe period ( (G) of FIG. 4).

This signal / D2BE is input to the NOR gate 17 while being input to the selection control stage S of the multiplexer 9 and the enable control stage / EN of the decoder 15, and thus the multiplexer 9 Since the input terminal 10 selects and outputs data of 1111, the decoder 10 enters the operation stop mode, and the decoder 15 is enabled.

Subsequently, when the second byte of the 2-byte instruction, that is, data, is input, the lower 4 bits of the output of the latch 8 are stored in the latch 4 in synchronization with the strobe signal STB ', and the data output from the latch 14. Is decoded by the decoder 15, and the m-th signal of the 2-byte command signal (2BD) of the decoded result is output (see (i) in FIG. 4), and the output signal is input to the NOR gate 17.

Therefore, the mth NOR gate 17 (the NOR gate is configured by the number of outputs of / 2BC (m = 16)) specified in the decoded signal (2BC), and / 2BC is inputted in common, and / D2BE and / DSTB are input in common. ) Outputs high to output the latch clock (/ 2CMD (m)) of the register as shown in FIG.

At this time, the output MIFB-D becomes data as the second byte of the two-byte command, is supplied to the input of the corresponding register, and latches the data as the clock / 2CMD (m).

Further, the command signal / 1BC (/ 2BC) is supplied as each enable signal / 1CMD-EN and / 2CMD-EN.

The clock (/ 1CMD (n), / 2CMD (m)) and the 2-byte enable signal / 2BE are input to the selection control terminal S of the multiplexer 19 through the encoder 18, Accordingly, the multiplexer 19 selects the state information STAT of the processing unit 5 according to each command and outputs it to the microcomputer as the sense signal SENSE, and the microcomputer decodes the sense signal SENSE to the digital servo IC side. You will be given a control command.

As described above, according to the present invention, since serial data is received from a microcomputer and converted into parallel data, commands are provided to each register as required, the servo IC can be miniaturized when the ASIC is manufactured. It is convenient to control the IC, and data can be provided to the servo IC, so it is easy to convert the digital servo IC to a desired characteristic.

Claims (1)

A serial / parallel converter 7 for receiving serial data / command information (SDI) and a clock (SDCLK) from a microcomputer and converting serial data into parallel data, a latch 8 for storing parallel 1-byte information, and a latch (8) a multiplexer 9 for selectively outputting the upper 4 bits of the output, a decoder 10 for decoding the output 1-byte or 2-byte instruction of the multiplexer 9, and a delay with the output of the decoder 10 D flip for synchronizing the strobe signal / DSTB and outputting the NOR gate 11 for outputting the latch clock (/ 1CMD (n)) of the register and the strobe signal / STB in synchronization with the main clock CLK. A flop 12, a delay unit 13 for delaying the synchronized strobe signal / STB, a latch 14 for storing the output lower 4 bit data of the latch 8, and a delayed 2-byte enable signal. Decoder 15 which decodes the latch 14 output in accordance with (/ D2BE), and the output 2 bytes of the decoder 10 A delay unit 16 for delaying the enable signal / 2BE by one strobe period, and a logic combination of the output data of the decoder 15 according to the delayed strobe signal / DSTB and the delayed 2-byte enable signal / D2BE. The NOR gate 17 for outputting the latch clock (/ 2CMD (m)) of the register, the latch clock (/ 1CMD (n), / 2CMD (m)) and the 2-byte enable signal (/ 2BE) Digital consisting of an encoder 18 and a multiplexer 19 which outputs a sense signal SENSE by combining the state information STAT from the processing unit 5 of the digital servo IC under the encoder 18 output control. Microcomputer interface device of servo IC.