KR940008294B1 - High speed data transmitting circuit with common input/output line - Google Patents

Abstract

The data transmission circuit gives speed-up based on using bit lines directly connected to the gates of output transistors during data transmission in dynamic RAM and gives large scale integration with common I/O lines. The circuit comprises bit lines BL, BL (65)(66) connected to a memory cell (51), transistors (61)(62)(63)(64) for data input, transistors (57)(58) for data output, transistors (53)(54)(59)(60) for separation of electric connection, a transistor (56) for electric discharge to make a voltage level applied to other channel an earth voltage level, a sense amplifier (55) for amplifying the voltage difference between the bit lines BL, BL (65)(66), a signal (CSL) for selecting a memory cell (51).

Description

High speed data transfer circuit with common input / output line

1 is an embodiment of a conventional data transmission circuit.

2 is another embodiment of a conventional data transfer circuit.

3 is a data transmission circuit having a common input / output line according to the present invention.

4 is a graph of output characteristics of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer circuit of a dynamic RAM in a semiconductor memory device, and more particularly, to a data transfer circuit suitable for high speed operation and high integration.

As semiconductor memory devices become more and more highly integrated, there is a need for high speed data input and output, and accurate data transfer is required. In order to meet the above requirements, the fast and accurate sensing operation of the bit line to which data is transmitted, the amplification capability of the sense amplifier that greatly amplifies the potential difference of the bit line, and the layout of each memory element must be balanced. Ham is well known in the field.

1 illustrates a conventional data transfer circuit. The components of FIG. 1 include the memory cells 9 and 11, the word lines 10 and 12, the first and second bit lines BL, (15) (16), and the first and second bit lines BL, (15) (16) sense transistors (7), isolation transistors (1) (2) (3) (4) separating the respective memory cells (9) and (11), and the first and second bits Input and output transistors 5 and 6 having one end of a channel connected to lines BL and BL 15 and 16, and input and output lines 13 and 14 connected to the respective input and output transistors 5 and 6, respectively. And the sense amplifier 8 of the input / output lines 13 and 14. A column select line (CSL) is connected to the control terminals of the input / output transistors 5 and 6, respectively.

The operation of FIG. 1 will be described. When a read operation of data stored in the memory cell 9 is performed, the isolation transistor 1 and 2 connected to the memory cell 9 are " turned on " 3) (4) "turns off".

The word line 10 of the memory cell 9 is selected to transmit data of the memory cell 9 to the first bit line BL 15 and the first and second bit lines BL, (15) The potential difference of (16) is enlarged through the sense amplifier (7). Then, the first and second bit lines BL, (15) The data transmitted to (16) is transferred to the input / output lines (13) and (14) through the input / output transistors (5) and (6), with the column select line (CSL) selected, and to the input / output sense amplifier (8). As a result, the potential of data lowered to the input / output line parasitic capacitance is increased again. However, the characteristics of the data transmission circuit, the first and second bit lines BL, (15) 16 and the input / output lines 13 and 14 are connected to the source and drain terminals of the input / output transistors 5 and 6. Accordingly, the column select lines CSL may include the first and second bit lines BL, (15) Since the potential difference in (16) should be selected after being sufficiently enlarged, a decrease in speed due to delay time is caused. Since the potential of the data transmitted to the input / output lines 13 and 14 passes through the input / output transistors 5 and 6, the voltage drop is reduced by the threshold voltage of the input / output transistors 5 and 6. Occurs. Further, when the input / output transistors 5 and 6 are 'turned on', the input / output lines 13 and 14 and the first and second bit lines BL, Since the parasitic capacitance is increased because the parasitic capacitance is increased, the difference in the data potential transmitted to the input / output lines 13 and 14 is further reduced, so that the sensing capability of the input / output line sense amplifier 8 is degraded.

Another conventional data transfer circuit is shown in FIG. 2 which supplements the disadvantages of the data transfer circuit of FIG. The data transfer circuit shown in FIG. 2 is a reference to the HITACHI 64M DRAM paper reported in the "1990 Symposium on VLSI Circuit". In FIG. 2, the memory cells 33, 34, isolation transistors 21, 22, 23, 24, and the first and second bit lines BL, (39) The configuration of the sense amplifier 32 in (40) is the same as the circuit of FIG. However, the difference between the second degree and the first degree is that the first and second bit lines BL, (39) 40 are connected to the gates of the output transistors 25 and 26, respectively. Thus, input lines 35 and 36 of data are provided and the first and second bit lines BL, (39) 40, and input transistors 29, 31, and output transistors 25, 36 for connecting the input lines 35, 36, and output lines 37, 38, respectively. do. And a transmission transistor (28) (30) for connecting the input lines (35) and (36) to the input transistors (29) and (31) under the control of a column select line (CSL), and the output line (37) ( 38 is provided with a transmission transistor 27 for connecting one end of the signal to a ground voltage terminal.

The operation of FIG. 2 will be described. In the case of reading data stored in the memory cell 33, the data of the memory cell 33 is amplified by the sense amplifier 32 through the isolation transistor 21 that is "turned on" and the output transistor 25. 26 are "turned on" and "turned off", respectively. In this case, when the column select line CSL is selected, the transmission transistor 27 is “turned on” and the output transistor 25 926 serves as a sense amplifier. The first and second bit lines BL, (39) The potential difference of the data of 40 is transmitted to the output lines 37 and 38 by the operation of the output transistors 25 and 26, and finally passes through the output sense amplifier 41. On the other hand, in the case of the operation of writing data to the memory cell 33, after the data is transferred to the data input lines 35 and 36, the input transistors 29 and 31 are " turned on " When the line csl is selected, the transmission transistors 28 and 30 connected to the input lines 35 and 36 are " turned on " so that the input lines 35 and 36 and the first and second bit lines are turned on. BL, (39) (40) is connected and data is transmitted. The data transmission circuit as shown in FIG. 2 includes first and second bit lines BL, (39) (40) is directly connected to the gates of the output transistors (25) and (26) to improve the output speed of the data, but the input line and the output line are required respectively, so that the number of transistors associated with the data input and output is too high integration problem do.

Accordingly, an object of the present invention is to provide a data transmission circuit suitable for high integration and having high speed of input / output of data.

In order to achieve the object of the present invention, the present invention provides a data transfer circuit in which input and output operations of data are controlled by a predetermined control signal, the first and second bit lines BL connected to memory cells; Complementary switching operation of the first and second driving transistors having a first and a second driving transistor connected to each control terminal, each channel connected between a ground voltage terminal and a pair of common data input and output lines. By the input and output operation of the data is characterized in that.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A data transmission circuit according to the present invention is shown in FIG. 3 and FIG. 3 is a circuit diagram of a data transfer circuit according to the present invention, wherein the data input / output lines 67 and 68 are a pair having complementary logic operations, and the first and second output transistors 57 First and second bit lines BL at the gates of 58, respectively, (65) 66 is connected and the first bitline BL 65 (or the second bitline) The first output transistor 57 (or the second output transistor 58) and the first input transistor pair 61, 62 (or the second input transistor pair 63, 64) connected to a 66. The input and output lines 67 and 68 are alternately connected to each other. 4 is a waveform diagram illustrating output characteristics of the third diagram, wherein the first and second bit lines BL, (65) The operating characteristics when the sensing operation of (66) occurs are shown.

The configuration of FIG. 3 will be described. In FIG. 3, the data transfer circuit according to the present invention includes a plurality of memory cells, first and second bit lines BL connected to the memory cells, And an input / output sense amplifier for amplifying the input / output of data, wherein the semiconductor integrated circuit performs data reading and writing operations of the memory cells according to a predetermined control signal. A pair of common input / output lines having complementary logic levels, the predetermined control signal connected to a control voltage, one end of a channel connected to a ground voltage terminal, and a discharge transistor for making a potential applied to the other end of the channel to a ground voltage level And a separation transistor stage in which the predetermined control signal is connected to a control voltage and one end of a channel is connected to the common input / output line, and a potential of the common input / output line is connected to a control voltage and the other end of the channel of the bit line and the separation transistor stage. An input transistor stage having a channel connected therebetween, First and second bitlines BL, And an output transistor stage having a potential of the channel connected between the other end of the channel of the discharge transistor and the other end of the channel of the isolation transistor stage.

In the above configuration, the column select line CSL signal is applied as a "high" signal as soon as the word line 52 is designated and the memory cell 51 is selected as shown in FIG. The discharge transistor 56 is formed of an enMOS transistor as an embodiment, and the isolation transistor stages 59 and 60 are connected to the pair of common input / output lines 67 and 68, one channel each and the column selection. Each of the first and second separations 59 and 60 having the line CSL signal as a common control voltage is used, and the components thereof are each constituted by enMOS transistors. The input transistor stages 61, 62, 63, and 64 are connected to the pair of common input / output lines 67 and 68, one for each control terminal, and each of the bit lines BL 65 and the second separation line. Each control terminal is connected to each of the first input transistor pairs 61 and 62 connected to a channel between the channels of the transistor 60 and the pair of common input / output lines 67 and 68, and the bit line A second input transistor pair 63 and 64 connected with a channel between the channel 66 and the channel of the first isolation transistor 59 is constituted of an enMOS transistor as an embodiment. The output transistor stages 57 and 58 are first outputs having a control terminal connected to the bit line BL 65 and having a channel connected between the discharge transistor 56 and the channel of the first isolation transistor 59. Transistor 57 and the bit line A control terminal is connected to the terminal 66, and the second output transistor 58 is connected between the discharge transistor 56 and the channel of the second isolation transistor 60. It consisted of a transistor. In FIG. 3, reference numerals 53 and 54 denote isolation transistors to separate electrical connections of respective memory cells in the memory cell array, and reference numeral 55 denotes the first and second bit lines BL, (65) A sense amplifier which amplifies the potential difference of (66), whose components are found to be the same as those known in the art.

The operation of the data transmission circuit according to the present invention will be described in detail with reference to FIG. Prior to the description, in the data transfer circuit according to the present invention, the first and second output transistors 57 and 58 are " turned on " 67) Note that it operates as a switching transistor that controls the current amplification of (68). Thus, for example, when the second output transistor 58 is "turned off", one of the data input / output lines 67 connected to the channel of the second output transistor 58 is electrically insulated from the ground voltage terminal. Thus, current amplification is performed at high speed. On the other hand, the input transistor stages 61, 62, 63, 64 are " turned on " only at the time of data input and " turned off " at the output of the data, for example. For example, when the potential of the first bit line BL 65 becomes "high", the pair of data input / output lines of which the potential of the first bit line BL 65 is precharged to 1 / 2VCC level are precharged. (67) The first input transistor pairs 61 and 62 are " turned off " because the signal of 68 is higher than the control voltage of the first input transistor pairs 61 and 62 applied as a control voltage. do. In this case, when the initial column select line (CSL) signal is "high" in the case of the second input transistor pair 63 (64), the gate voltage and the source of the second input transistor pair 63 (64) are sourced. As the voltage difference between the input voltages is smaller than the threshold voltage and is " turned off " and over time, 64 of the second input transistor pairs becomes an input / output line 68 and a bit line. Since 66 is kept at the voltage difference smaller than the threshold voltage and simultaneously goes down to the "low" level, it is "turned off" continuously, and 63 is the input / output line 68 and the bit line. Since the 66 is conducted, the input / output line 68 is lowered to the "low" level more quickly by the amplification operation of the sense amplifier 55.

First, the operation of reading data of the memory cell is described. In this case, when the word line 52 is selected, the bit line BL 65 is charged by charge sharing between the memory cell 51 and the bit line BL 65. Compared to 66, the state becomes "high". Subsequently, when a column select line (CSL) signal is selected, the first output transistor 57 is “turned on” before the second output transistor 58 so that the input / output line connected to the channel of the first output transistor 57 ( 68 starts to be made to the ground voltage level through the discharging transistor 56, and as the sense amplifier 55 is operated, the bit line BL 65 is at the "high" level and the BL 66 is "low". As the level is lowered, the current flowing through the first output transistor 57 becomes larger, while the second output transistor 58 is gradually "turned off" so that the potential difference between the input and output lines 67 and 68 is greater. do. In this case, the first input transistor pairs 61 and 62 are “turned off” as described above to prevent the first bit line BL 65 from communicating with the first input / output line 67 and the first input transistor pair 61. The potential of the bit line BL 65 is maintained continuously. As shown in FIG. 4, the first and second bit lines BL, As in the sensing operation of 65, the amplification operation of the common data input / output lines 67 and 68 also proceeds rapidly, indicating that data is output at high speed. Next, a case where data write operation is performed to the memory cell 51 will be described. The data loaded on the first or second input / output lines 67 and 68 are transferred to the first and second bit lines BL through the first or second input transistor pairs 61 and 62; (65) and (66). For example, assuming that data is loaded on the first input / output line 67, the potential of the first bit line BL 65 rises to "high" and the first output transistor 57 is "turned on".

The potential of the second input / output line 68 then falls to the ground voltage terminal and the second output transistor 58 is " turned off ". Therefore, the potential of the first input / output line 67 is applied only to the first bit line BL 65 to perform a write operation to the memory cell 51.

The above-described data transfer circuit according to the present invention of FIG. 3 is one embodiment in which the spirit of the present invention is realized, and the respective transport elements may be changed without departing from the spirit of the present invention. It will be easy to understand.

According to the above, in the data transfer circuit according to the present invention, the data transfer speed is improved by connecting the bit line directly to the gate of an output transistor during data transfer from the bit line to the data input / output line. By using a common solution to the problem of the high integration of the circuit using a separate input line and the output line of the conventional can be solved.

Claims (9)

A plurality of memory cells each storing predetermined data, a bit line BL connected to the memory cells, And the bit line BL, In a semiconductor integrated circuit having a sense amplifier for amplifying a potential difference between them, a data transfer circuit for reading or writing data into a memory cell in response to a predetermined control signal, wherein the input or output of the data is transmitted and A pair of common input / output lines having complementary logic operations, a channel is connected in parallel between the first input / output line and the bit line BL among the pair of common input / output lines, and gates are respectively connected to the pair of common input / output lines correspondingly. A pair of first input transistors corresponding to the data when the data is input through a pair of common input / output lines and correspondingly transmitted to the bit line BL; a second input / output line and the bit line of the pair of common input / output lines; And a second input channel connected in parallel with each other, and a pair of gates connected to the pair of common input / output lines, respectively, to transmit the data to the bit line BL when data is input through the pair of common input / output lines. A discharge transistor for discharging a voltage introduced into the other end of the channel in response to an input of the control signal by connecting a pair of transistors, one end of a channel to a ground voltage terminal, and a gate connected to the control signal, and a channel of the discharge transistor. A channel is connected between the other end of the second input line and the bit line A first output transistor having a gate connected to the first output transistor, a channel connected between the other end of the channel of the discharge transistor and the first input / output line, and the bit line And an output transistor pair comprising a second output transistor connected to a gate thereof. 2. The data transmission circuit according to claim 1, wherein the first and second output transistors perform a "turn on" operation with each other when the data is output. 2. The data transmission circuit according to claim 1, wherein the first and second input transistor pairs perform " turn on " only when the data is input. The method of claim 1, wherein the bit line BL, The first and second output transistors corresponding to the bit line BL, One of the pair of common input / output lines corresponding to the channel of the first or second output transistor gated to the one bit line when one of the terminals becomes the ground level is insulated from the ground voltage terminal. Characterized in that the data transmission circuit. The control circuit of claim 1, wherein the data transmission circuit is controlled by the control signal and is connected to the connection path between the channels of the first and second output transistors and the pair of common input / output lines. And a second isolation transistor. A plurality of memory cells storing respective predetermined data, a bit line BL connected to the memory cells, And the bit line BL, In a semiconductor integrated circuit having a sense amplifier for amplifying a potential difference between them, a data transfer circuit for reading or writing data into a memory cell in response to a predetermined column select line signal, wherein the input or output of the data is transferred. And a pair of common input / output lines with complementary logic operations, one end of a channel connected to a ground voltage terminal, and a gate connected to the column select signal to discharge a voltage flowing into the other end of the channel in response to the input of the column select signal. And a bit line connected between the discharge transistor and a first input / output line of the pair of common input / output lines and the other end of the channel of the discharge transistor. A second output having a gate connected to the first output transistor, a channel connected between the channel of the discharge transistor and a second input / output line of the pair of common input / output lines, and a gate connected to the bit line BL; An output transistor stage comprising a transistor, a first isolation transistor having a channel connected to a channel of the first output transistor and the first input / output line, and gate-connected to the column selection signal, a channel of the second output transistor, and the A separate transistor stage comprising a second isolation transistor having a channel connected to an input / output line and gate-connected to the column selection signal, the first input / output line and the bit line; Channels are connected in parallel between and the gates are connected to the pair of common I / O lines one by one, so that the bit lines are input when data is input through the pair of common I / O lines. A pair of first input transistor stages corresponding to each other, and a channel are connected in parallel between the second input / output line and the bit line BL, and gates are correspondingly connected to the pair of common input / output lines, respectively. And a pair of second input transistor stages corresponding to the data when the data is input through the input / output line and correspondingly transmitted to the bit line BL. 7. The data transfer circuit of claim 6, wherein each of the first and second isolation transistors is formed of an NMOS transistor. The bit line of claim 6, wherein each of the control terminals is connected to the pair of pain input / output lines one by one. And a first NMOS transistor pair having a channel connected between a channel of the second isolation transistor and a control terminal connected to the pair of common input / output lines one by one, and between the bit line BL and the channel of the first isolation transistor. And a second NMOS transistor pair connected to the channel. 10. The data transfer circuit according to claim 8, wherein the first and second enMOS transistor pairs are " turned on " only when the data is input.