KR100908515B1 - Data sensing circuit - Google Patents

Abstract

The present invention relates to a data sensing circuit, comprising: a first high isolation transistor and a first row isolation transistor connected to a first bit line, a second high isolation transistor and a second row isolation transistor connected to a second bit line; A sense amplifier having first and second nodes connected to a connection point of a first high isolation transistor and a first row isolation transistor and a connection point of the second high isolation transistor and a second low isolation transistor, respectively; first and second nodes of the sense amplifier First and second high isolation transistors and the first and second low isolation transistors each having a higher threshold than a transistor having a low threshold voltage and a transistor having a normal threshold voltage. It consists of a negative word line transistor with a low threshold voltage.

Description

Data sensing circuit {Circuit for sensing data}             

1 is a circuit diagram for explaining a data sensing circuit according to the present invention.

2 is a graph illustrating the leakage current (Ioff) characteristics of the data sensing circuit according to the present invention.

3 is a graph illustrating a current (Idsat) characteristic of a data sensing circuit according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: sense amplifier

20: precharge means

The present invention relates to a data sensing circuit used in a semiconductor memory device, and more particularly, to a data sensing circuit capable of reducing a leakage current and improving an operating speed.

In general, a semiconductor memory device includes a memory cell array in which a plurality of memory cells are connected between a word line and a bit line, and various peripheral circuits for storing or reading information in each memory cell of the memory cell array.

To store information in a memory cell, a program bias voltage is applied to gates and drains of the memory cell through word lines and bit lines, respectively, so that the threshold voltage rises above a predetermined level. A sensing circuit is used to sense the amount of current flowing through the bit line while the read bias voltage is applied to the gate and the drain of the corresponding memory cell through the bit line.

The data sensing circuit is largely comprised of a sense amplifier, a memory cell for sensing and amplifying the amount of current flowing through the bit line of the memory cell and the amount of current flowing through the bit line of the reference memory cell. A switching unit for electrically insulating the connected bit line BL and the bit bar line BL / connected to the reference memory cell, and a transfer switching unit for transferring the output of the sense amplifier to the pad unit. .

The sense amplifier is generally configured in a cross coupled form. The switching unit is usually composed of a transistor having a low threshold voltage or a normal threshold voltage.

In a device having a gate width of 0.117 μm, the switching unit is configured with a transistor having a low threshold voltage of about 0.2 V. In this case, the block selection speed is increased, but the leakage current (Ioff) characteristic is deteriorated. Will be affected. Therefore, in the device having a gate width of 0.97 μm, the switching unit is configured by using a transistor having a normal threshold voltage of about 0.5 V. In this case, the leakage current characteristic is improved, but the operation speed characteristic of the device is deteriorated. .

Accordingly, the present invention provides a data sensing circuit capable of solving the above-mentioned disadvantages by constructing a switching unit using a negative word line transistor having a higher threshold voltage than a transistor having a low threshold voltage and having a lower threshold voltage than a transistor having a normal threshold voltage. The purpose is.

The present invention for achieving the above object is the first high isolation transistor and the first row isolation transistor connected to the first bit line, the second high isolation transistor and the second row isolation transistor connected to the second bit line, A sense amplifier having first and second nodes connected to a connection point of a first high isolation transistor and a first row isolation transistor and a connection point of the second high isolation transistor and a second low isolation transistor, respectively; first and second nodes of the sense amplifier First and second high isolation transistors and the first and second low isolation transistors each having a higher threshold than a transistor having a low threshold voltage and a transistor having a normal threshold voltage. It is characterized by consisting of a negative word line transistor having a low threshold voltage.

Hereinafter, a data sensing circuit according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating a data sensing circuit according to the present invention.

The first high isolation transistor HN1 and the first row isolation transistor LN1 are connected in series between the bit lines BL connected to the memory cell, and the second high isolation transistor between the bit bar lines BL / connected to the reference memory cell. HN2 and the second row isolation transistor LN2 are connected in series.

A sense amplifier is connected to the connection point J1 of the first high isolation transistor HN1 and the first row isolation transistor LN1 and the connection point J2 of the second high isolation transistor HN2 and the second row isolation transistor LN2. First and second nodes of (10) are connected, respectively, and the first and second transfer transistors SN1 and SN2 operated by the transmission signal YI to the first and second nodes of the sense amplifier 10, respectively. Are respectively connected.

The other terminal of the first transfer transistor SN1 is connected to the first transmission line LDB connected to the output pad, and the other terminal of the second transfer transistor SN2 is connected to the second transmission line SN2 connected to the output pad. ) Is connected. Precharge means 20 is connected between the bit line BL and the bit bar line BL / to make the potentials of the bit line BL and the bit bar line BL / at the same level.

The sense amplifier 10 is connected in series between a line RTO providing a positive potential and a line SB providing a ground potential, and each of the P-MOS transistors P1 and N whose gates are connected to a second node. A MOS transistor N1 and the lines RTO and SB are connected in series and each gate comprises a P-MOS transistor P2 and an N-MOS transistor N2 connected to a first node.

In the present invention, the first and second high isolation transistors HN1 and HN2 constituting the first switching unit and the first and second row isolation transistors LN1 and LN2 constituting the second switching unit have a low threshold voltage. It is composed of a negative word line transistor having a threshold voltage higher than a transistor and lower than a transistor having a normal threshold voltage, for example, about 0.3 to 0.4V.

The operation of the data sensing circuit according to the present invention will be described with reference to FIG. 1 as follows.

When both transistors of the first switching unit and the second switching unit are turned on by the high isolation signal BISH and the low isolation signal BISL, the bit line BL is connected to the selected memory cell, and the bit bar line BL / The sensing operation is started by being connected to the reference memory cell.

At this time, when the information is stored in the memory cell, the amount of current flowing through the bit line BL is smaller than the amount of current flowing through the bit bar line BL /, and thus the first node is connected to the first node by the operation of the sense amplifier 20. The voltage of the ground potential provided through SB is applied, and the voltage of the positive potential provided through the line RTO is applied to the second node, and the voltage of the first node is applied to the transistor according to the transmission signal YI. The voltage is transmitted to the transmission line LDB through SN1 and the voltage of the second node is transferred to the transmission line LDB / through the transistor SN2 according to the transmission signal YI.

When the sensing operation is completed, the bit line BL and the bit bar line BL / are shorted with each other by the operation of the precharge means 20. The potential of is maintained at the same level of about 1V.

In the present invention, a negative word line transistor having a higher threshold voltage than a transistor having a low threshold voltage and a lower threshold voltage than a transistor having a normal threshold voltage is used. The negative word line transistor is turned on when a high voltage (Vpp) of about 3.2V is applied to the gate, thereby raising the threshold voltage to 0.3 to 0.4V, and is turned off when a negative low voltage (Vbbw) of about -0.3V is applied. (Turn off) to lower the threshold voltage to about 0V. Therefore, the operating characteristics of the device may be improved by solving the leakage current (Ioff) problem that occurs when using a transistor having a low threshold voltage and the operation speed decrease problem that occurs when using a transistor having a normal threshold voltage.

As shown in FIG. 2, since the voltage Vgs between the gate and the source is 0 V in the state where the memory cell is not selected, a leakage current Ioff is generated as in the A part, but the present invention is not limited thereto. When using a negative word line transistor, as shown in FIG. 2, since the voltage Vgs between the gate and the source is -0.2 to -0.7V, the leakage current Ioff is not generated as in the B part. Therefore, using a negative word line transistor having a lower threshold voltage than a transistor having a normal threshold voltage increases the current Idsat by about 25% and improves the speed tREF as shown in FIG. 3 for a device having a gate width of 0.145 μm. Was measured.

As described above, in the present invention, the switching unit is configured by using a negative word line transistor having a higher threshold voltage than a transistor having a low threshold voltage and having a lower threshold voltage than a transistor having a normal threshold voltage. This can be improved.

Claims (4)

A first high isolation transistor and a first row isolation transistor connected to the first bit line, A second high isolation transistor and a second row isolation transistor connected to a second bit line, A sense amplifier having first and second nodes connected to the connection point of the first high isolation transistor and the first row isolation transistor and the connection point of the second high isolation transistor and the second row isolation transistor, respectively, First and second transfer transistors respectively connected to first and second nodes of the sense amplifier, Wherein the first and second high isolation transistors and the first and second low isolation transistors are formed of a negative word line transistor having a higher threshold voltage than a transistor having a low threshold voltage and having a lower threshold voltage than a transistor having a normal threshold voltage. Data sensing circuit. The data sensing circuit of claim 1, wherein the threshold voltage of the negative word line transistor is 0.3 to 0.4V. 2. The data sensing circuit of claim 1, further comprising bit line precharge means connected between the first and second bit lines to equalize the potentials of the first and second bit lines. 2. The transistor of claim 1, wherein the sense amplifier is connected in series between a first line providing a positive potential and a second line providing a ground potential, each gate having a first P-MOS transistor connected to the second node; First N-MOS transistor, And a second P-MOS transistor and a second N-MOS transistor connected in series between the first line and the second line, each gate connected to the first node.

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