KR20000045390A - Sdram with enhanced pre-charging operation - Google Patents

Abstract

PURPOSE: A sDRAM(synchronous dynamic random access memory) is provided to increase a speed of an operating cycle time by removing a separate time of pre-charging operation. CONSTITUTION: In an SDRAM, each cell array block(Block#0,Block#1) has each separated pre-charge circuit(PRE#0,PRE#1). The pre-charge circuits are controlled and operated each by separated control signals of pre-charge(blp#0,blp#1). The SDRAM is performed a read operation and a pre-charge operation at the same time. Thereby, a separated operating time of pre-charge is removed and an operating cycle time is quickened by internally performing the pre-charge without a separated pre-charge command.

Description

Sync DRAM with improved precharge

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a Synchronous DRAM, which is a very high speed memory, and more particularly, to a Synchronous DRAM further improved in speed by improving a precharge operation.

The speed of semiconductor memory devices is increasing rapidly. In particular, the conventional DRAM (DRAM) is limited in speed, so the sync DRAM, which is a synchronous DRAM that operates in synchronization with a clock, represents a high speed memory.

In this sink DRAM, an additional time is allocated for precharging a cell array block that has performed a read operation after a read operation and before a new row active operation command is input. The operation cycle time of the sink DRAM is delayed by that time, which causes a problem in high speed operation.

If you look at this in detail as follows.

1 is a cell array circuit diagram of a conventional sink DRAM, FIG. 2 is a block diagram illustrating the flow of the block control signal of FIG. 1, and FIG. 3 is a block diagram illustrating the flow of the row address signal of FIG. 1. 4 is a detailed circuit diagram of the actctl block of FIG. 2, FIG. 5 is a detailed circuit diagram of the sendly block of FIG. 2, and FIG. 6 is a detailed circuit diagram of the blocntrl block of FIG. 2. The read operation timing diagram of FIG. 1 is illustrated in FIG. 7.

First, referring to FIG. 7, a conventional sink DRAM having a cell array structure as shown in FIG. 1 may be a PCG associated with an ACT related to an active mode, a read related to a read operation, and a precharge. Consists of.

As shown in FIG. 1, the circuit configuration includes a memory cell, a sense amplifier S / A, a bit line and its complementary bit lines bl and blb, a word line wl, and data. It is composed of a cell array block having a shared S / A structure composed of bus lines db, dbb, and the like.

In this configuration, as shown in FIG. 7, the state of each node before the ACT command is input is examined. First, wl and yi become logic "low". The bit line precharge signal blp and the separate transistor control signals bish and bisl become logic "high". The bit lines bl and blb, bl-s and blb-s, and the sense amplifier drive signals rto and sb become arbitrary reference potentials (i.e., vblp in FIG. 1). The data bus lines db and dbb are in a stand-by state at any constant potential level. This state is called a precharge state.

At this time, if the ACT command is input, the circuit logic is configured so that one word line wl transitions to logic "high" and transfers the potential stored in the cell capacitor to the bit line bl to slightly increase the potential of the bit line bl. To make it or to lower it slightly. Next, rto and sb precharged with vblp are shifted to potential levels of logic "high" and "low", and the potential change of the bit line bl and the potential of blb are compared, so that the potential of bl is determined by the potential of the cell capacitor. If it is slightly raised, the potential of bl is shifted to the potential level of rto and blb to the potential level of sb. On the other hand, when the potential of bl is slightly lowered by the potential of the cell capacitor, the potential of bl is shifted to the potential level of sb and the potential of blb to the potential level of rto. Such an operation is called a sensing operation of the sense amplifier.

On the other hand, the block in which the word line wl is selected while the ACT instruction is executed must be electrically separated from other blocks sharing the sense amplifier S / A. This is achieved by using signals of bish and bisl. For example, in FIG. 1, when word line wl in BLOCK # 0 is selected, bish maintains logic "high" and bisl transitions to logic "low" so that bit lines BL and BLB of BLOCK # 1 from sense amplifier S / A. Isolate.

If the Read command, which is a read command, is inputted, yi is shifted to a logic "high" level to transfer the data of the bit lines bl and blb sensed by the ACT command to the data bus lines db and dbb.

Then, when the PCG, which is a precharge command, is input, the ACT transitions the changed levels to the precharge state.

FIG. 2 is a block diagram of signals for controlling the cell array block of FIG. 1. In FIG. 2, the detailed circuit is illustrated in FIG. 4. When the ACT command is input, the bnkact becomes a logic “high” pulse to transition the rowctl signal to the logic “high” level state. bnkact becomes a logic "low" pulse to transition the rowctl signal to a logic "low" level state.

The snd signal in FIG. 2 is a signal obtained by delaying the rowctl signal for a predetermined time, and the circuit configuration thereof is as shown in FIG. In FIG. 5, the dly block configures logic to signal predly as an input terminal to the output terminal postdly with time delay while maintaining the same level. When the snd signal transitions to the logic "high" level, rto and sb transition to the logic "high" and "low" at which time the sensing operation begins.

If the selected wl is at BLOCK # 0 when the ACT command is input in FIG. 2, the BLOCK # 0 signal is at the logic "high" level. If the selected wordline wl is at BLOCK # 1, the BLOCK # 1 signal is at the logic "high" level. To transition.

An example of the blocntrl circuit of FIG. 2 is shown in FIG. 6, where the BLOCK # 0 or BLOCK # 1 signal goes to a logic "high" level when a ACT command is input, causing the bisl or bish to transition to a logic "low" level. . And blp transitions to a logic "low" level.

This state is maintained while the Read command is being executed. When a PCG command is input, rowctl becomes the logic "low" level, making the snd signal the logic "low" level, and the BLOCK # 0 and BLOCK # 1 signals are logic. At the "low" level, bish, bisl, and blp are all at the logic "high" level. By bringing blp to a logic " high " level, bl / blb, bl-s / blb-s, rto, and sb transition to the vblp potential level.

3 is a block diagram of a flow of address signals for controlling a word line wl signal. When an ACT command is input, some of the ax01, ax <2: n> signals transition to a logic "high" level, and logic is arranged to transition wl to a logic "high" level, while a PCG command is input. The logic is structured so that rowctl goes to the logic "low" level, so that the wordline wl transitions to the logic "low" level.

As described above, in the conventional sink DRAM having the structure of FIG. 1, the signal levels such as word lines wl, bisl, bish, bl / blb, and blp are maintained at the level transitioned by the ACT command while the Read command is performed. For this reason, this state had to be reduced to the precharge state by the input of a separate PCG instruction. Therefore, a separate precharge time was required in the sink DRAM, and the operation cycle time of the sink DRAM was delayed by that time, which impeded high speed operation.

Accordingly, an object of the present invention is to provide a sink DRAM in which an extra precharge operation time is eliminated to speed up an operation cycle time.

Another object of the present invention is to provide a sink DRAM in which precharge is performed internally without a separate precharge command.

1 is a cell array circuit diagram of a conventional sink DRAM,

2 is a block diagram illustrating the flow of a block control signal of FIG. 1;

3 is a block diagram illustrating the flow of a row address signal of FIG. 1;

4 is a detailed circuit diagram of the actctl block of FIG. 2;

5 is a detailed circuit diagram of the sendly block of FIG. 2;

6 is a detailed circuit diagram of the blocntrl block of FIG. 2;

7 is a timing diagram of a read operation of FIG. 1;

8 is a cell array circuit diagram of a sink DRAM according to the present invention;

9 is a block diagram illustrating the flow of a block control signal of FIG. 8;

10 is a detailed circuit diagram of the actctl block of FIG. 9;

11 is a detailed circuit diagram of the sendly block of FIG. 9;

12 is a detailed circuit diagram of the blocntrl block of FIG. 9;

FIG. 13 is a read operation timing diagram of FIG. 8. FIG.

<Description of Major Symbols in Drawing>

Block # 0: first cell array block # 1: second cell array block

ISO # 0: First Separate Transistor Section ISO # 1: Second Separate Transistor Section

PRE # 0: first precharge means PRE # 1: second precharge means

S / A: Sense Amplifier

According to an aspect of the present invention, a sink DRAM includes: a pair of bit lines commonly connected to a first cell array block, a second cell array block, the first cell array block, and a second cell array block; A first isolation transistor unit coupled to the first cell array block side and operating in response to an input of a first split control signal, and connected to a second cell array block side to respond to an input of a second split control signal; And a first precharge means formed on a bit line between the first cell array block and the first cell transistor block to operate in response to an input of a first precharge signal. Second precharge means formed on a bit line between the second cell array block and the second isolation transistor unit to operate in response to an input of a second precharge signal; 2 split transistor And a sense DRAM having a sense amplifier formed on bit lines between the stud portions.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

8 is a cell array circuit diagram of a sink DRAM according to the present invention. The structural feature is a pair which is commonly connected to the first cell array block Block # 0, the second cell array block Block # 1, and the first cell array block Block # 0 and the second cell array block Block # 1. Bit lines bl and blb of &lt; RTI ID = 0.0 &gt;, &lt; / RTI &gt; a first isolation transistor section ISO # 0 coupled to the first cell array block Block # 0 side and operating in response to input of a bish signal, and a second cell array block Block # 1 side. Is formed on the bit line between the second isolation transistor section ISO # 1 and the first cell array block Block # 0 and the first isolation transistor section ISO # 0, which are connected close to the second transistor and operate in response to the input of the bisl signal. And a first precharge means PRE # 0 operating in response to an input of a blp # 0 signal, and a bit line between the second cell array block Block # 1 and the second isolation transistor unit ISO # 1. second precharge means PRE # 1 operating in response to an input of a blp # 1 signal, and the first isolation transistor section ISO # 0 Second isolation transistor unit comprises a sense amplifier S / A to be formed on the bit lines between the ISO # 1.

Referring to the above configuration, in the sink DRAM according to the present invention, each cell array block Block # 0 and Block # 1 have their own precharge circuits PRE # 0 and PRE # 1, and these precharge circuits PRE # 0 And PRE # 1 are controlled by the respective precharge control signals blp # 0 and blp # 1. Through this configuration, the sink DRAM according to the present invention is capable of simultaneously performing a read operation and a precharge operation, and a detailed description thereof will continue.

FIG. 9 is a block diagram illustrating a flow of a block control signal for performing internal precharge of FIG. 8. 9, it can be seen that the read signal is newly supplied to the input of the actctl block and the sendly block, respectively. In order to implement the present invention, a read command must be supplied as described above.

In FIG. 9, the read signal is a signal that transitions to the H level when the Read command is input. When the read command is completed, the read signal transitions to a logic “low” level. Using this signal, the rowctl signal is controlled through the actctl block, the snd signal is controlled through the sendly block, and the bish, blp, blp # 0, and blp # 1 signals are controlled through the blocntrl block.

10 is a detailed circuit diagram of the actctl block of FIG. 9. In terms of the configuration, a means for controlling the read command is newly added as in the dotted block 10-1. Thus, the Read command is input so that the read signal is at a logic "high" level, thereby making rowctl at a logic "low" level. From this, the word line wl transitions to a logic "low" level according to the flow configuration of FIG.

FIG. 11 is a detailed circuit diagram of the sendly block of FIG. 9. Also in the configuration, it can be seen that the means controlled by the read command is newly added as in the dotted block 11-1. 9 shows an example of the sensdly block. After the rctctl transitions to the logic "low" level due to the input of the Read command, the snd signal is logic the moment the read command is completed and the read signal transitions to the logic "low" level. Transition to the "low" level. When snd is at the logic "low" level, blp is at the logic "high" level, causing rto, sb, and bl-s / bib-s to transition to the reference potential vblp level.

12 is a detailed circuit diagram of the blocntrl block of FIG. 8. This circuit is newly implemented to control the levels of bl / blb, bish, and bisl while executing the Read command. Referring to the configuration, a means 12-1, which is newly controlled by Block # 0 and a read signal, has been added to the first separation control signal bish generating unit, and a block # 1 and read signal is newly added to the second separation control signal bisl generation unit. Added by means of control 12-2. The first cell array block precharge signal blp # 0 generator 12-3 and the second cell array block precharge signal blp # 1 generator 12-3 are newly implemented using the bit line precharge signal blp. With this configuration, for example, when the selected wl is in Block # 0, when the ACT command is input, bisl transitions to the logic "low" level and bish to the logic "high" level, where blp # 0, blp # 1, The blp signal transitions to a logic "low" level. When the read command is input, the bish transitions to the logic "low" level, while the blp # 0 signal transitions to the logic "high" level, separating Block # 0 from the sense amplifier S / A and breaking the bitline bl of Block # 0. Transition / blb to vblp level.

FIG. 13 is a timing diagram of a read operation of FIG. 8. In FIG. 13, region 13-1 is a time when the word line wl becomes a logic "high" to activate the cell transistor and perform sensing in the sense amplifier S / A after charge sharing between the cell capacitor and the bit line. It is a section indicating. A region 13-2 shows an interval in which the array block selected by the separate control signals bish and bisl is separated from the sense amplifier S / A, the word line wl is turned off to a logic “low”, and then internally precharged. The region 13-3 is a section for internally precharging the sense amplifiers S / A and S / A nodes after the read operation is completed. On the other hand, area 13-4 is a section in which a burst read operation is performed.

By using the method illustrated in FIG. 13, the cycle time of the command in the sink DRAM requiring high speed can be shortened by performing internal precharge without input of a separate precharge command.

Although the foregoing has been described with respect to embodiments of the present invention, those skilled in the art will understand that various implementations are possible within the scope of the technical idea of the present invention.

As described above, the present invention has the effect of precharging internally without a separate precharge command, thereby eliminating a separate precharge operation time and speeding up an operation cycle time.

Claims (1)

In sink DRAM, A first cell array block, A second cell array block, A pair of bit lines connected in common to the first cell array block and the second cell array block; A first separation transistor unit connected to the first cell array block and operated in response to an input of a first separation control signal; A second separation transistor unit connected to the second cell array block side and operated in response to the input of the second separation control signal; First precharge means formed on a bit line between the first cell array block and the first isolation transistor unit to operate in response to an input of a first precharge signal; Second precharge means formed on a bit line between the second cell array block and the second isolation transistor unit to operate in response to an input of a second precharge signal; And a sense amplifier formed on a bit line between the first isolation transistor portion and the second isolation transistor portion. Sink DRAM characterized by simultaneously performing precharge and read operations.