KR940008146B1 - Dual pot memory - Google Patents

Abstract

a multiplexing circuit having a first transmission gate stage, and a second transmission gate stage for complementarily switching-operating with the first transmission gate stage; a predecoder for predecoding a column address; a column gate for connecting a data input/output line and a bit line; and a column selector for controlling a switching operation of the column gate, thereby improving high integration.

Description

Dual Port Memory with Blocklight

1 is a circuit diagram of a block light performing means according to the prior art.

2 is a circuit diagram of a column selector of the block light performing means according to the present invention.

3 is a block diagram of multiplexing means of 2LSB column addresses and input data according to the present invention;

4 is an embodiment of FIG.

5 is a block diagram showing generation of each clock signal according to the present invention.

6 is a data input buffer circuit diagram according to the present invention.

7 is a timing diagram of each clock signal according to the present invention.

* Explanation of symbols for the main parts of the drawings

DSF: fine special function pin

DT / OE: Data transmission / output enable signal (pin)

WB / WE: Light Mask / Light Enable Signal (Pin)

RAS ': Low address strobe delay signal

CAS ': Column address strobe delay signal

BW: Block light enable signal

DILPB: Inverted data input latch pulse

WB: Masking Enable Signal

WI / Oi: External data input / output signal (pin)

The present invention relates to dual port memory, and more particularly, to a dual port memory having a block write function.

A dual port memory, as is well known, is a memory having both a random access port and a serial access port. Among the functions that can be performed, for example, a memory array includes four memory arrays. It has a block write function that can write 16 bits of data at a time when 4 bits are accessed when divided into blocks and once access operation is performed. This function is considerably effective in the case of clear operation of a window, for example, on a monitor in the image processing field, and is effectively used when writing a large amount of data.

In this regard, a circuit diagram for performing a block light function according to the related art is shown in FIG. 1. The circuit shown in FIG. 1 is referred to US Patent Nos. 4, 807 and 189. For details, such as the generation of signals applied to the circuit shown in FIG. Please.

In FIG. 1, the portion indicated by the dotted line block 204 is a column selector, and a multiplexing of 2LSB (least significant bit) column addresses and four input data (43-05, 43-2, 43-4, 43-6) (normalization or block light) is performed through (multiplexing). The LSB is a concept of "lowest bit" and generally refers to "0" and "1" in this field. In FIG. 1, AY1 and AY0, which are the least significant bits of the column address, become LSB. When the circuit of FIG. 1 is in the block write mode, the 2LSB column addresses AY1 and AY0 should be replaced with the four input data 43-0, 43-2, 43-4, and 43-6. That is, the output from which the 2LSB column addresses AY1 and AY0 are decoded is disabled, and instead, four input data 43-4 can be independently controlled to control four memory cells that can be decoded by the two column addresses. 0, 43-2, 43-4, 43-6). The circuit of FIG. 1 illustrates a method of multiplexing two LSB column addresses and four input data. As shown, the remaining column addresses (AY2, ..., AY7) except for the 2LSB column addresses (AY1, AY0) are predecoded through a predecoder. The 2LSB column addresses (AY1, AY0) are decoded separately through the decoder 210 and each decoding output (214n, ..., 214n + 3) is connected to the bit line through the first transfer gate (212n, ..., 212n + 3). It is connected to the control voltage of the column gates 220n, ..., 220n + 3 for connecting to the O line. The four input data 43-0, ... 43-6 are connected to the column gates 220n, ..., 220n + 3 through the second transfer gates 216n, ..., 216n + 3. The four input data 43-0,..., 43-6 can independently control the four column addresses. In the above method, the column addressing is performed using only the column address, and the 2LSB column addresses 2Y1 and 2Y0 and the four input data 43-0, in the process of controlling the column gates 220n, ..., 220n + 3. … 43-6) is multiplexed.

However, in the method of performing multiplexing as in the circuit of FIG. 1, the second transfer gates 216n, ..., 216n + 3 are required as many as the number of bit lines, and the block write enable clock signal ( BW) and the number of the first and gates 206 for decoding the column address are needed by one fourth of the number of the bit lines. Considering that the circuit of FIG. 1 (i.e., the column selector) is a circuit for selecting only four memory cells, the circuit for selecting a myriad of other memory cells included in the chip has the configuration as shown in FIG. It exists innumerably, which causes a problem that the occupied area is considerably large in the layout of the chip, which is disadvantageous for high integration.

Accordingly, an object of the present invention is to provide a dual-port memory having a column selector which has a compact structure of a circuit for performing a block light function and occupies a small area of the chip.

In order to achieve the above object of the present invention, the present invention provides a dual port memory having a normal light mode and a block height mode, respectively; A first transmission gate stage for inputting the decoded signal of the two least significant bit column addresses and outputting the input in response to a control input of the block light enable signal enabled in the block light mode; and an input output from the data input buffer. Multiplexing means for inputting data and outputting the input in response to a control input of the block light enable signal, the second transmission gate stage being configured to switch complementarily with the first transmission gate stage; A predecoder for inputting a column address specifying a column of a memory cell and predecoding the column address; A column gate connecting the data input / output line and the bit line; And a column selector for inputting an output signal of the multiplexing means and transmitting the input to the column gate in response to the output signal of the predecoder to control the switching operation of the column gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a column selector according to the present invention. FIG. 3 shows a decoding means of a column decoding output signal applied to the column selector circuit of FIG. 2 as a block diagram. Shown in the figure. 5 shows a data input buffer for outputting the input data of FIG. FIG. 6 illustrates the generation of each clock signal applied to the circuit according to the present invention, and a timing diagram of each clock signal is shown in FIG.

2 shows a column selector circuit as block write means according to the present invention. The configuration includes the MOS transistors T1, T2, which supply the input signals 10n, 10n + 1, 10n + 2, 10n + 3 to the gates of the column gates MT1, MT2, MT3, MT4 in response to the output signals of the predecoder. T3, T4).

The configuration of FIG. 4, which is an embodiment of the multiplexing means 100 in FIG. 3, is a block light enable in which two least significant bit column addresses AY0, AY1 input a decoded signal and enable this input in the block light mode. signal Input the first transmission gate stage (TM2, TM4, TM6, TM8) output in response to the control input of the BW, and input data (DI0, DI1, DI2, DI3) output from the data input buffer. Light Enable Signal The second transmission gate stage TM1, TM3, TM5, TM7 is configured to output in response to a control input of the BW, and is configured to switch to and complement the first transmission gate stage TM2, TM4, TM6, TM8. There is a phase characteristic. As can be seen in the configuration shown in FIG. 4, the first transmission gate stage TM2, TM4, TM6, TM8 is a block write enable signal. When the BW is deactivated, it is " turned on " and the second transmission gate stages TM1, TM3, TM5, and TM7 are block light enable signals. Turn "on" when the BW is active.

When performing the block write function according to the present invention, four input data are used instead of the 2LSB column address, and the written data is generated from the color register 51 of FIG. 6 and each data is also masked. The mask is collectively referred to as "write-per-bit" operation, which is a function for selectively writing only a predetermined desired bit in the array block, in which the predetermined bit executes writing and no writing other than the bit. May be). Control logic and data input buffers for realizing this are shown in FIG. 5 and FIG.

The value of the color register 51 in FIG. 6 is D0 to D7 (not shown) in the color register 51 due to a LOR signal (see FIG. 5) generated during a load color register cycle. ) Is stored as an output signal CRi (CR0 to CR7). For example, in the case of normal light, the block light enable signal The NWi signal is connected to the D signal because BW is an inactive " low " signal, and in the case of a block light, the CRi signal is connected to the D signal. Masking function is Every cycle The BWi signal and the light per bit enable signal that are latched at the falling edge It is controlled by the M signal of the masking line which AND-gated the WB signal. In other words, when the M signal is a "low" signal in an inactive state, the output of the DIN signal is disabled, so that a write operation does not occur. The DIi replacing 2LSB column address at the time of block write is the NWi signal and the NWi signal in which D0 to D7 are latched. Generated by end gating 57 the BW signal.

Then, at the time of decoding the 2LSB column addresses AY0 and AY1 and the DIi signal, as shown in FIG. Generated by end gating 57 the BW signal. Then, at the time of decoding the 2LSB column addresses (AY0, AY1) and the DIi signal, as shown in FIG. The DIi and the 2LSB column addresses AY0 and AY1 are replaced by multiplexing using a BW signal. As shown in FIG. 4, an embodiment of a circuit for multiplexing the DIi signal and the 2LSB column addresses AY0 and AY1, when not in the block light mode, The BW signal is applied as a "low" signal in an inactive state, and only the transmission gates TM2, TM4, TM6, and TM8 are "turned on" to block the output of the DIi (DI1, DI2, DI3, DI4) signal in FIG. Enable output of the 2LSB column addresses AY0, AY1. On the contrary, in the block light mode, The BW signal is applied as an active "high" signal (see FIG. 7 above) so that only the transmission gates TM1, TM3, TM5, TM7 are "turned on". Therefore, the output of the DIi (DI1, DI2, DI3, DI4) signal is enabled and the output of the 2LSB column addresses AY0, AY1 is cut off. Thus, the DIi signal is replaced with the 2LSB column addresses AY0 and AY1. Accordingly, the signal output from the FIG. 4 circuit controls the column gates MT1, MT2, MT3, MT4 as shown in FIG. 2. As can be seen in the circuit shown in FIG. 2, since the normal light and the block light can be executed as the signal output from the circuit of FIG. 4, the number of bit lines shown in the circuit of FIG. The layout area is considerably reduced by eliminating the need for the second transfer gate terminal of X and the AND gate as much as 1/4 of the bit line. This makes it possible to compactly implement the circuit arrangement provided to perform the block light mode, thereby realizing a reduction in the occupied area in the chip.

The circuits of the column selector circuit according to the present invention shown in FIG. 2 and the associated circuits of FIGS. 3, 4, 5, and 6, respectively, are optimally implemented to realize the spirit of the present invention. It is an example, and it should be understood that the related circuit may be configured differently within the technical scope that can be realized by the above-mentioned second article.

As described above, the present invention multiplexes before the decoding operation of the dual port memory (at the same time as the normal write operation) 2LSB column address and input data, thereby compactly realizing the components of each circuit accordingly, resulting in high integration. It has the effect of improving.

Claims (5)

A dual port memory having a normal light mode and a block light mode as an operation mode, respectively, wherein two least significant bit column addresses input a decoded signal and control the block light enable signal enabled in the block light mode. A first transmission gate stage for outputting in response to an input and input data output from a data input buffer and outputting the input in response to a control input of the block write enable signal, and switching complementarily with the first transmission gate stage A multiplexing means each including a second transmission gate stage configured to operate, a predecoder for inputting and predecoding a column address specifying a column of a memory cell, a column gate for connecting a data input / output line and a bit line; , The output signal of the multiplexing means Input and to send the input in response to the output signal of the predecoder to the column gate dual-port memory, characterized in that each comprising a column select to control a switching operation of the column gate. The method of claim 1, wherein in the multiplexing means, only the second transmission gate stage is "turned on" in the block light operation mode, and only the first transmission gate stage is "turned on" in the normal light operation mode. Dual port memory. The method of claim 1, wherein the column selector comprises a MOS transistor comprising a control terminal connected to an output signal of the predecoder and a channel formed between an output terminal of the multiplexing means and a control terminal of the column gate. Dual port memory. In a dual-port memory having at least a block light mode as an operation mode of a chip, a data input buffer for inputting data supplied from the outside of the chip and shaping it to an internal signal level, and a signal in which two least significant bit column addresses are decoded are input. And a first transmission gate stage for outputting the input in response to the deactivation input of the block light mode enable signal, input data output from the data input buffer, and inputting this input to the activation input of the block light mode enable signal. A multiplexing means each comprising a second transmission gate stage for outputting in response to the second transmission gate; and an output signal of the multiplexing means, the input signal being transmitted to the column gate in response to the output signal of the predecoder, and the switching operation of the column gate. Each of the column selector to control the Dual-port memory, characterized by. The dual port memory of claim 4, wherein the predecoder inputs and decodes the remaining column addresses except for the two least significant bit column addresses among the column addresses input to the chip.