KR940008086A - Manufacturing method of programmable semiconductor switching device and manufacturing method of semiconductor array using same - Google Patents

Manufacturing method of programmable semiconductor switching device and manufacturing method of semiconductor array using same Download PDF

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KR940008086A
KR940008086A KR1019920016606A KR920016606A KR940008086A KR 940008086 A KR940008086 A KR 940008086A KR 1019920016606 A KR1019920016606 A KR 1019920016606A KR 920016606 A KR920016606 A KR 920016606A KR 940008086 A KR940008086 A KR 940008086A
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South Korea
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layer
forming
conductive
manufacturing
insulating
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KR1019920016606A
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Korean (ko)
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조흥식
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김광호
삼성전자 주식회사
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Priority to KR1019920016606A priority Critical patent/KR940008086A/en
Publication of KR940008086A publication Critical patent/KR940008086A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

프로그래머블 반도체 스위칭 장치의 제조방법에 있어서, 제1도전형을 형성하는 단계, 제1도전체 위에 절연층을 형성하고 개구부를 형성하는 단계, 제1도전층이 드러난 개구부에 산화층 및/또는 질화층의 제1절연층과, 이위에 비전동성 실리콘층과 이위에 산화층 및/또는 질화층의 제2절연층으로 된 유전체 층을 형성하는 단계, 유전체층위에 제2의 도전층을 형성하는 단계로 이루어져 형성됨을 특징으로 하는 프로그래머블 반도체 스위칭 장치의 제조방법.A method of manufacturing a programmable semiconductor switching device, comprising: forming a first conductive type, forming an insulating layer and forming an opening on the first conductor, and forming an oxide layer and / or a nitride layer in the opening where the first conductive layer is exposed. Forming a dielectric layer comprising a first insulating layer, a non-electromagnetic silicon layer thereon, and a second insulating layer thereon of an oxide layer and / or a nitride layer, and forming a second conductive layer over the dielectric layer. A method of manufacturing a programmable semiconductor switching device.

Description

프로그래머블 반도체 스위칭 장치의 제조방법 및 이를 사용한 반도체 어레이 제조방법Manufacturing method of programmable semiconductor switching device and manufacturing method of semiconductor array using same

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도 (a)∼(d)는 본 발명에 따른 프로그래머블 반도체 스위칭 장치를 사용한 프로그래머블 반도체 어레이 제조 수순을 설명하는 고정도.1 (a) to (d) are high accuracy for explaining a procedure of manufacturing a programmable semiconductor array using the programmable semiconductor switching device according to the present invention.

제2도(a)∼(b)는 본발명에 따른 프로그래머블 반도체 스위칭 장치의 프로그램을 행하는 것을 특징으로 하는 도면이다.2A to 2B are diagrams illustrating the programming of a programmable semiconductor switching device according to the present invention.

Claims (8)

프로그래머블 반도체 스위칭 장치의 제조방법에 있어서, 제1도전층을 형성하는 단계, 제1도전체 위에 절연층을 형성하는 개구부를 형성하는 단계, 제1도전층이 드러난 개구부에 제1정영층고, 이 위에 비전도성 실리콘층과 이 위에 제2절연층으로 된 유전체층을 형성하는 단계, 유전체 층 위에 제2의 도전층을 형성하는 단계로 이루어져 형성됨을 특징으로 한 프로그래머블 반도체 스위칭 장치의 제조방법.A method of manufacturing a programmable semiconductor switching device, the method comprising: forming a first conductive layer, forming an opening for forming an insulating layer on the first conductor, a first spirit layer in the opening where the first conductive layer is exposed, and A method of manufacturing a programmable semiconductor switching device, comprising forming a nonconductive silicon layer and a dielectric layer comprising a second insulating layer thereon, and forming a second conductive layer over the dielectric layer. 제1항에 있어서, 상기 유전체 층의 비전도성 실리콘층 위에 및/또는 질화층의 절연층을 또한 포함하여 형성됨을 특징으로 한 프로그래머블 반도체 스위칭 장치의 제조방법.The method of claim 1, further comprising an insulating layer of a nitride layer and / or on a non-conductive silicon layer of the dielectric layer. 제1항 또는 제2항에 있어서, 상기 제1도전층은 반도체 기판내에 형성된 확산 영역이며, 상기 제1 및/또는 제2 절연층은 NO또는 ONO층이며, 상기 비전도성 실리콘층은 다결정 실리콘이거나 또는 비정질 실리콘층이며, 상기 제2도전층은 금속층인 것을 특징으로 하는 프로그래머블 반도체 스위칭 장치의 제조방법.3. The method of claim 1, wherein the first conductive layer is a diffusion region formed in a semiconductor substrate, the first and / or second insulating layers are NO or ONO layers, and the nonconductive silicon layer is polycrystalline silicon. Or an amorphous silicon layer, and wherein the second conductive layer is a metal layer. 제3항에 있어서, 상기 비전도성 실리콘층은 비소 또는 인의 불순물이 함유된 것임을 특징으로 하는 프로그래머블 반도체 스위칭 장치의 제조방법.The method of claim 3, wherein the nonconductive silicon layer contains an arsenic or phosphorous impurity. 프로그래머블 반도체 스위칭 장치를 구비한 프로그래머블 반도체 어레이의 제조법에 이있어서, 소자분리된 반도체 기판 또는 웰의 활성영역에 게이트 전극과 소오스/드레인 영역을 위한 불순물 영역을 형성하는 단계, 기판전면에 걸쳐 절연층을 형성하고 상기 불순물층을 제1도전층으로하여 절연층에 개구부를 형성하는 단계, 개구부의 드러난 제1도전층에 산화층 및/또는 질화층의 제1 절연층과, 이 위에 비전도성 실리콘 층로된 패턴 형성된 유전체 층을 형성하는 단계, 추전체층 상에 프로그래밍 전압을 인가하기 위한 신호 라인으로서 제2도전층을 형성하는 단계로 이루어짐을 특징으로 하는 프로그래밍 반도체 스위칭 장치를 구비한 프로그래머블 반도체 어레이 제조방법.A method of fabricating a programmable semiconductor array with a programmable semiconductor switching device, the method comprising: forming impurity regions for gate electrodes and source / drain regions in an active region of a device-separated semiconductor substrate or well; Forming an opening in the insulating layer using the impurity layer as a first conductive layer, a first insulating layer of an oxide layer and / or a nitride layer on the exposed first conductive layer of the opening, and a nonconductive silicon layer thereon. Forming a formed dielectric layer, and forming a second conductive layer as a signal line for applying a programming voltage on the piezoelectric layer. 제5항에 있어서, 상기 유전체 층의 비전도성 실리콘층 위헤 산화층 및/또는 질화층의 제2절연층을 또한 포함하여 형성됨을 특징으로 하는 프로그래밍 반도체 스위칭 장치를 구비한 프로그래머블 반도체 어레이 제조방법.6. The method of claim 5, further comprising a second insulating layer of an oxide layer and / or a nitride layer over the nonconductive silicon layer of the dielectric layer. 제5항 또는 제6항에 있어서, 상기 제1도전층은 반도체 기판이거나 기판내에 형성된 웰 영역이며, 상기 제1 및/또는 제2절연층은 NO 또는 ONO층이며, 상기 비전도성 실리콘층을 다결정 실리콘이거나 또는 비정질 실리콘층이며, 상기 제2도전층은 금속층인 것을 특징으로 하는 프로그래밍 반도체 스위칭 장치를 구비한 프로그래머블 반도체 어레이 제조방법.The non-conductive silicon layer of claim 5, wherein the first conductive layer is a semiconductor substrate or a well region formed in the substrate, and the first and / or second insulating layers are NO or ONO layers. And a silicon layer or an amorphous silicon layer, and wherein the second conductive layer is a metal layer. 제7항에 있어서, 상기 비전도성 실리콘층은 비소 또는 인의 불순물이 함유된 것임을 특징으로 하는 프로그래밍 반도체 스위칭 장치를 구비한 프로그래머블 반도체 어레이 제조방법.The method of claim 7, wherein the nonconductive silicon layer contains an arsenic or phosphorous impurity. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920016606A 1992-09-09 1992-09-09 Manufacturing method of programmable semiconductor switching device and manufacturing method of semiconductor array using same KR940008086A (en)

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