KR940007703Y1 - Bios circuit of vertical deflection part - Google Patents

Bios circuit of vertical deflection part Download PDF

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Publication number
KR940007703Y1
KR940007703Y1 KR2019890009136U KR890009136U KR940007703Y1 KR 940007703 Y1 KR940007703 Y1 KR 940007703Y1 KR 2019890009136 U KR2019890009136 U KR 2019890009136U KR 890009136 U KR890009136 U KR 890009136U KR 940007703 Y1 KR940007703 Y1 KR 940007703Y1
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South Korea
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transistor
vertical deflection
current
resistor
base
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KR2019890009136U
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Korean (ko)
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KR910001800U (en
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이문기
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주식회사 금성사
이헌조
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/18—Generation of supply voltages, in combination with electron beam deflecting
    • H04N3/19—Arrangements or assemblies in supply circuits for the purpose of withstanding high voltages

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Details Of Television Scanning (AREA)
  • Video Image Reproduction Devices For Color Tv Systems (AREA)

Abstract

내용 없음.No content.

Description

TV수직편향부 바이어스회로TV vertical deflection bias circuit

제 1 도는 종래의 TV수직편향부 바이어스회로도.1 is a conventional TV vertical deflection bias circuit diagram.

제 2 도는 본 고안에 따른 TV수직편향부 바이어스 회로도.2 is a TV vertical deflection bias circuit diagram according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

Z : 제너다이오드 Q1, Q2, QA-QC: 트랜지스터Z: Zener Diodes Q 1 , Q 2 , Q A -Q C : Transistor

R, R1-R4, RA-RB: 저항 1 : 수직편향부R, R 1 -R 4 , R A -R B : Resistance 1: Vertical Deflection

본 고안은 TV수직편향부 바이어스회로에 관한 것으로, 특히 바이어스회로에 보호기능을 부가하여 신뢰성을 향상시킨 TV수직편향부 바이어스회로에 관한 것이다.The present invention relates to a TV vertical deflection bias circuit, and more particularly, to a TV vertical deflection bias circuit having improved reliability by adding protection to the bias circuit.

종래의 TV수직편향부 바이어스회로는 제 1 도에서 보는 바와같다.The conventional TV vertical deflection bias circuit is as shown in FIG.

먼저 그 구성을 보면 전원(Vcc)은 저항(R)을 거쳐 제너다이오드(Z)의 캐소우드와 저항(R4)의 일측 및 수직편향부(1)로 인가되고 제너다이오드(Z)의 애노우드는 저항(R1, R2)의 접속점에 연결되고 저항(R2)의 다른 일측은 트랜지스터(Q1)의 베이스와 연결되고 트랜지스터(Q1)의 콜렉터는 저항(R4)과 트랜지스터(Q2)의 콜렉터에 공통연결되고 트랜지스터(Q1)의 에미터는 트랜지스터(Q2)의 베이스와 저항(R3)에 공통연결되고 저항(R1), (R3)의 일측과 트랜지스터(Q2)의 에미터 및 수직편향부(1)의 일단은 그라운드(GND)와 연결된다.First of all, the configuration of the power supply Vcc is applied to the cathode of the zener diode Z and the one side and the vertical deflection portion 1 of the resistor R 4 through the resistor R and the anode of the zener diode Z. lifting resistance (R 1, R 2) the collector of the connection at the junction of and the other side of the resistor (R 2) is connected to the base of the transistor (Q 1) and the transistor (Q 1) is a resistance (R 4) and the transistor (Q 2) of the collector commonly connected are commonly connected to the transistor (emitter of the transistor (the base and the resistance (R 3) of the Q 2) Q 1) to and resistance (R 1), (R 3) one side of the transistor (Q 2 The emitter and one end of the vertical deflection portion 1 is connected to the ground GND.

상기 구성회로의 작용상태를 보면, 수직편향부(1)의 바이어스 VB=VBE·Q1+VBE·Q2+VZ으로 결정된다(VBE·Q1: 트랜지스터(Q1)의 베이스-에미터전압, VBE·Q2: 트랜지스터(Q2)의 베이스에미터전압, VZ: 제너다이오드(Z)의 제너전압).In the working state of the configuration circuit, the bias of the vertical deflection portion 1 is determined as V B = V BE Q 1 + V BE Q 2 + V Z (V BE Q 1 : transistor Q 1 ). Base-emitter voltage, V BE .Q 2 : base emitter voltage of transistor Q 2 , V Z : zener voltage of zener diode (Z)).

이때 제너다이오드(Z)를 흐르는 전류 IZ=(VBE·Q1+VBE·Q2)/R1이고 트랜지스터(Q1)의 콜렉터전류 I1=(VBE·Q2)/R3, 저항(R)을 흐르는 전류 ICC=(VCC-VB)/R이다.At this time, the current flowing through the zener diode (Z) I Z = (V BEQ 1 + V BEQ 2 ) / R 1 and the collector current I 1 = (V BEQQ 2 ) / R 3 of the transistor Q 1 , The current I CC = (V CC -V B ) / R flowing through the resistor R.

따라서 트랜지스터(Q1)의 콜렉터전류 I2=ICC-IZ-I1-IB로 결정된다.Therefore, the collector current I 2 = I CC -I Z -I 1 -I B of the transistor Q 1 is determined.

그런데 상기와 같은 종래 TV수직편항부 바이어스회로에서는 트랜지스터(Q2)의 콜렉터전류 I2는 대략 ICC-IB로 결정되는데 경우에 따라 트랜지스터(Q2)에 과전류가 흐르게 되어 트랜지스터(Q2)가 파손되는 경우가 많이 발생하는 단점이 있었다.However, the conventional TV vertical side hangbu bias circuit, the collector current I 2 of the transistor (Q 2) is the over-current to the transistor (Q 2) to flow in some cases is determined by approximately I CC -I B transistor (Q 2), such as the There was a disadvantage that a lot of cases are broken.

본 고안은 이러한 단점을 해결하기 위해 안출된 것으로 첨부도면을 참조하여 상세히 설명하면 다음과 같다.The present invention has been devised to solve these disadvantages and will be described in detail with reference to the accompanying drawings.

먼저 제 2 도에서 그 구성을 보면, 전원(Vcc)은 저항(R)을 통해 제너다이오드(Z)의 캐소우드단과 저항(R4) 및 수직편향부(1)로 인가되고 제너다이오드(Z)의 애노우드는 저항(R1)을 거쳐서는 그라운드(GND)로 연결되고 저항(R2)을 거쳐서는 트랜지스터(Q1)의 베이스와 연결되고 트랜지스터(Q1)의 콜렉터는 저항(R4)(RA)이 접속점과 연결되는 동시에 트랜지스터(QA)의 에미터와 연결되고 트랜지스터(Q1)의 에미터는 저항(R3)을 통해 그라운드(GND)로 연결되는 동시에 트랜지스터(QB)의 콜렉터와 트랜지스터(Q2)의 베이스에 공통연결되고 트랜지스터(Q2, QB)의 에미터는 그라운드(GND)로 연결되는 트랜지스터(Q2)의 콜렉터는 저항(RA)과 트랜지스터(QA)의 베이스에 공통연결되고 트랜지스터(QA)의 콜렉터는 트랜지스터(QC)의 콜렉터와 베이스에 동시연결되고 또 트랜지스터(QC)의 베이스는 저항(RB)을 통해 그라운드와 연결되는 동시에 트랜지스터(QB)의 베이스와 연결되고 트랜지스터(QC)의 에미터와 수직편향부(1)의 일측은 그라운드(GND)로 연결된다.First, as shown in FIG. 2, the power supply Vcc is applied to the cathode terminal of the zener diode Z, the resistor R 4 , and the vertical deflection portion 1 through the resistor R, and the zener diode Z is applied. The anode of is connected to ground (GND) via resistor (R 1 ), to the base of transistor (Q 1 ) via resistor (R 2 ), and the collector of transistor (Q 1 ) is resistor (R 4 ). (R A ) is connected to the junction at the same time as the emitter of transistor Q A and the emitter of transistor Q 1 is connected to ground (GND) via resistor R 3 and at the same time of transistor Q B the collector of the collector and the transistor (Q 2) connected in common to the base and the transistor transistor (Q 2) is connected to the emitter of a ground (GND) of the (Q 2, Q B) of a resistor (R a) and the transistor (Q a) The collector of transistor Q A is simultaneously connected to the collector and base of transistor Q C. One side of and another transistor (Q C) base resistor (R B) at the same time connected to ground via being connected to the base of the transistor (Q B) transistor (Q C), the emitter and the vertical deflection unit (1) of the It is connected to ground (GND).

상기 구성회로의 작용상태를 설명하면 아래와 같다.The operational state of the configuration circuit will be described below.

수직편향부(1)의 바이어스 VB는 종래 회로에서와 마찬가지로 VB=VBE·Q1+VBE·Q2+VZ(VBE·Q1) : 트랜지스터(Q1)의 베이스에이터전압, VBE·Q2: 트랜지스터(Q2)의 베이스에미터전압, VZ: 제너다이오드(Z)의 제너전압)이다.Base Actuator voltage of the transistor (Q 1): bias V B of the vertical deflection unit (1) as in the conventional circuit V B = V BE · Q 1 + V BE · Q 2 + V Z (V BE · Q 1) , V BE .Q 2 : base emitter voltage of transistor Q 2 , and V Z : zener voltage of zener diode Z).

정상적인 상태에서는 트랜지스터(QA-QC)가 "오프"상태에 있다가 트랜지스터(Q2)에 일정전류이상의 과전류가 흐르게 되어 저항(RA)에 트랜지스터(Q2)를 "온"시킬 수 있는 이상의 전압(대략 0.7V)이 걸리게 되면 트랜지스터(QA)가 온하게 되고 따라서 트랜지스터(QA, QC)도 "온"상태가 된다.A normal state, the transistor (Q A -Q C) is "off" state is in the transistor (Q 2) on a constant current over an overcurrent flows to the resistor (R A) transistor capable of "on" a (Q 2) When the above voltage (approximately 0.7 V) is applied, the transistor Q A is turned on and thus the transistors Q A and Q C are also turned on.

트랜지스터(QA, QC)는 트랜지스터(Q2)의 베이스에 DC(직류)적으로 네가티브 피드백(Neqative feed back)되므로 트랜지스터(Q2)로는 일정전류이상의 전류가 흐르지 않고 제한된다.Roneun transistor (Q A, Q C) is a transistor (Q 2), so a DC (direct current) typically negative feedback (Neqative feed back) to the base transistor (Q 2) of the current is limited to not more than a certain current to flow.

그리고 과전류는 트랜지스터(QA)를 통하여 트랜지스터(QC) 및 트랜지스터(QB)로 흐르게 되고 또 트랜지스터(QB)가 "온"되면서 트랜지스터(Q1)을 통한 전류가 저항(R3) 및 트랜지스터(QB)로 빠지게 된다.The overcurrent flows through the transistor Q A to the transistor Q C and the transistor Q B , and when the transistor Q B is "on", the current through the transistor Q 1 causes the resistor R 3 and The transistor Q B is taken out.

즉 트랜지스터(Q2)에 과전류가 흐르게 되면 트랜지스터(QA, QC)가 동작되어 트랜지스터(QA) 및 트랜지스터(QC), 저항(RB)으로 과전류가 분담되어 흐르므로 트랜지스터(Q2)로는 일정전류 이상의 과전류가 제한되고 종래에는 트랜지스터(Q1)에 흐르는 전류가 VBE·Q2/R3로 고정되었으나 본 고안에서는 트랜지스터(QB)가 "온"되면서 트랜지스터(Q1)에 VBE·Q2/R3이상의 전류가 흘릴 수 있다.That is, when the the transistor (Q 2) over-current flows through transistors (Q A, Q C) the operation transistor (Q A) and a transistor (Q C), resistance (R B) to so flow is over-current is shared transistor (Q 2 ) Is limited to overcurrent above a certain current, and conventionally, the current flowing through the transistor Q 1 is fixed to V BE · Q 2 / R 3. However, in the present invention, the transistor Q B is “on” and thus the transistor Q 1 Current above V BE · Q 2 / R 3 can flow.

따라서 본 고안은 트랜지스터(Q2)의 과전류를 제한시키고 다른 통로로 전류를 흐르게 함으로서 트랜지스터(Q2)의 파손을 방지하여 IC가 불량이 되는 것을 막아주는 효과가 있다.Thus, the present design has the effect that by limiting the over-current of the transistor (Q 2) and to prevent damage to the transistor (Q 2) by flowing a current in the other passage prevents the IC is defective.

Claims (1)

수직편향부(1)의 바이어스(Bias)전압을 결정하는 트랜지스터(Q1, Q2), 제너다이오드(Z)와, 상기 트랜지스터(Q2)에 과전류가 흐를 때 동작하여 트랜지스터(QB, QC)를 동작시키는 트랜지스터(QA)의 동작에 따라 연동되어 트랜지스터(Q2)의 과전류를 제한하는 트랜지스터(QB, QC)를 포함하여 구성된 것을 특징으로 하는 TV의 수직편향부 바이어스회로.The transistors Q 1 and Q 2 and the zener diode Z, which determine the bias voltage of the vertical deflection portion 1, and the transistor Q 2 operate when an overcurrent flows to the transistors Q B and Q. C) the operation of the transistor (Q a) are linked in accordance with the operation transistor (Q 2) that is configured by a transistor (Q B, Q C) for limiting the over-current vertical deflection of a TV unit, characterized in the bias circuit of the.
KR2019890009136U 1989-06-29 1989-06-29 Bios circuit of vertical deflection part KR940007703Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019890009136U KR940007703Y1 (en) 1989-06-29 1989-06-29 Bios circuit of vertical deflection part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019890009136U KR940007703Y1 (en) 1989-06-29 1989-06-29 Bios circuit of vertical deflection part

Publications (2)

Publication Number Publication Date
KR910001800U KR910001800U (en) 1991-01-25
KR940007703Y1 true KR940007703Y1 (en) 1994-10-22

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019890009136U KR940007703Y1 (en) 1989-06-29 1989-06-29 Bios circuit of vertical deflection part

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Publication number Publication date
KR910001800U (en) 1991-01-25

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