KR940007283Y1 - Access processing logic in dual-port memory - Google Patents

Abstract

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Description

Virtual continuous access processing logic in dual port memory

1 is a main block diagram of a computer system using a general dual port memory.

2 is a reference diagram of dual port memory operation in FIG.

3 is a more detailed example of FIG.

4 is a block diagram of a PC system equipped with the virtual continuous access processing logic of the present invention.

5 is an embodiment of FIG.

6 is a reference diagram of the operating state of FIG.

* Explanation of symbols for main parts of the drawings

1: virtual continuous access processing logic 1a, 1b: address driver

Ic: Adder

The present invention relates to a computer system using dual port memory, and more particularly, to virtual continuous access processing logic designed to efficiently support the use and management of a ring buffer in such dual port memory.

Dual-port memory is a memory system whose operation can be accessed at different times by the system CPU and the controller. This memory is a ring-buffer operation that allows the controller to continuously access the memory and to continuously access the memory in address order. The CPU is included.

In one example, a typical type of such a system is shown in FIG.

Here, the system CPU 21, the dual port memory 22, and the controller 23, which share the data bus DB, the address bus AB, and the control bus CB, are connected to the controller 23. The transmitter 24 for communication processing with the outside is connected.

In addition, as shown in FIG. 3 of the system of FIG.

Here, logic is provided between the bus drivers 22a, 22b, 22c and the address latch 22d between the DB, AB, CB and the memory 22.

However, in such a conventional technique, when the memory 22 is used, some of the blocks below the ring buffer 22A, as shown in FIG. 2, must be kept in an actual empty space that cannot be used as a ring buffer, thereby resulting in a ring buffer 22A. There is a problem that it is impossible to make full use of the memory area, and the computer processing efficiency is lowered by performing the access operation while recopying the accessed packets in the address order.

For example, in such a system, four blocks of packets 1-4 written by the controller 23 as shown in FIG. 2 are transferred from the IC of FIG. 2C, which is the last part of the ring buffer 22A. If started, this packet must be fragmented.

This is because when the CPU 21 reads the packet, the CPU 21 processes the packets in the address order, so that the packets of the address area before the IC are copied to the remaining part of (b), and these are read continuously in the address order. This is because nagi is treated as a task.

Therefore, in such a conventional computer system, it is difficult to avoid such inefficiency of memory operation and processing efficiency.

The present invention has been devised to solve such a problem in the related art, and in particular, it is not necessary for the ring buffer in the memory of such a system to secure the remaining area of the empty space for recopy, etc., and the recopy operation also needs to be performed. Therefore, it is possible to provide virtual continuous access processing logic to the dual port memory to maximize the memory utilization of the system and achieve the good processing efficiency.

Further features of the present invention will be understood by examining this in more detail with an embodiment drawing of the present invention.

That is, FIG. 4 shows a PC system equipped with the virtual continuous access processing logic 1 according to the present invention.

In this case, when the packet is normal in the ring buffer 22A of the memory 22 between the data bus DB, the address bus AV, the control bus CB, and the dual port memory 22, it is processed in the normal address procedure and loaded on the memory 22 side. When the partitioned data has to be partitioned, the virtual continuous access processing logic 1 which is accessible by the virtual address is connected.

Incidentally, the virtual continuous access processing logic 1 has shown a specific embodiment thereof as shown in FIG.

Here, the bus driver 1a when the data loaded in the memory 22 is not allocated to the divided area in the environment where the partitioning operation is to be performed, the bus driver 1b when it is allocated to the divided area, and The 4-bit adder Ic for continuously connecting the divided packets is connected to the memory 22 side.

The present invention of such a configuration is as follows.

That is, in the virtual continuous access processing logic 1 of the present invention, when the data loaded by the controller 23 in the ring buffer 22A of the memory 22 is allocated to the partition area, the partition processing operation by recopy is required. The virtual address is assigned to have a packet of consecutive addresses from the packet of the initial address area of the partition.

At this time, the shift address value is added in the 4-bit adder 1c so as to have the predetermined upper address of the address outputted to the bus driver 1a and the sixth degree consecutive packet of the packet of the divided region as shown in FIG. The virtual address is formed through the driver 1b.

Thereafter, the CPU 21 performs the access operation as if the divided battle of the ring buffer corresponding to the address is not divided.

When the ring buffer packet is in the normal address order, the CPU 21 performs normal access processing via the bus drivers 22a, 1a, and 22c.

The present invention does not require a recopy operation due to address reallocation without the need for freeing space for split packets when accessing the ring buffer in dual port memory in a computer system using dual port memory. It is an advantageous feature that it is possible to have an efficient use of memory and to ensure a good processing efficiency.

Claims (2)

In the computer system including the dual port memory 22, the system CPU 21, the controller 23, the address driver 22a, the address latch 22d, etc., which are operated by the ring buffer 22A, the CPU 21 On the bus of the memory 22 and the controller 23, the packet written by the controller 23 in the ring buffer of the memory 22 is normally processed in the normal address order, and is virtually allocated when the packet is divided in the normal address order. A virtual serial access processing logic of dual port memory characterized by a configuration having a virtual continuous access processing logic (1) for generating and processing an address. The virtual continuous access processing logic (1) according to claim 1, wherein the virtual continuous access processing logic (1) includes a configuration including an address driver (1a) in a normal state, an adder (1c) and a virtual address driver (1d) for generating virtual addresses in a split state. Features virtual continuous access processing logic with dual port memory.