KR940006924B1 - Semiconductor memory device with redundancy circuit - Google Patents

Abstract

The circuit comprises normal cell arrays for saving data, normal decoders for indicating the selected memory cell, redundant memory cell arrays for replacing incorrect cells, redundant decoders for indicating replacing memory cells, and a repair circuit for enabling normal decoders in case of normal operation and enabling redundant decoders in case of repair operation. The repair circuit comprises an input part which has two inputs from external address and output of fuse circuits, a transfer part, and outputs of an output part which are connected with one input of normal decoders and redundant decoders.

Description

Semiconductor memory device having a repair circuit

1 is a repair circuit according to the prior art.

2 is an embodiment of a repair circuit according to the present invention.

3 is another embodiment of a repair circuit according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a repair circuit that performs a redundancy function.

The trend of higher integration and higher capacity of semiconductor memory devices has increased the failure rate of each memory cell in a chip. Thus, the configuration of redundant circuits and redundant memory cell arrays for replacing defective memory cells with non-defective memory cells has become essential in all current semiconductor memory devices. Redundant operation occurs when a memory cell in the normal memory cell array occurs as a defective cell by redundantly arranging spares (also called "replace" or "redundant") rows and columns other than the normal memory cell array. Is performed by selecting the spare rows and columns instead of the rows and columns for selecting the defective cells. The operation of performing the above operation is a redundant decoder, and whether or not the normal decoder and the redundant decoder are enabled is a repair circuit. In this field, a number of names are commonly used in this field. In general, when the redundant decoder is enabled, laser cutting is appropriately performed according to an address signal to decode a fuse included in the repair circuit. Is performed.

A conventional repair circuit is shown in FIG. FIG. 1 (a) is a circuit diagram of a conventional repair circuit and FIG. 1 (b) is an operation timing diagram according to FIG. The drawing disclosed in FIG. 1 (a) shows only a repair circuit in a semiconductor memory device, other than which is well known.

In FIG. 1 (a), MF1 to MF4 are enabled fuses, and a bad cell is generated so that when the repair operation is performed, the output of the address to be decoded is enabled. F1 to F16 are fuses for transmitting an address to be decoded, and all but the fuses connected to the address to be decoded are cut during the repair operation to block the output of the address other than the address to be decoded. G1 to G16 are pass gates (also called "pass gates" or "transfer gates"), which are " turned on " during the repair operation and are otherwise turned " turned off ". RA0 to RA3, RB0 to RB3, RC0 to RC3, and RD0 to RD3 are addresses output from a predecoder (not shown), respectively, of which addresses addresses specifying bad cells. In Fig. 1 (a), AT, BT, CT, and DT are signals output from the predecoder, RA0 to RA3, RB0 to RB3, RC0 to RC3, and RD0 to RD3, respectively, through the pass gates G1 to G16. In the case of AT, it is one signal output through this selected fuse, leaving only the fuse suitable for the bad address from the input of four signals RA0 to RA3, and in the case of BT, from the input of four signals RB0 to RB3. One signal is output through this selected fuse, leaving only the appropriate fuse for the bad address.In the case of CT, the signal is output through this selected fuse, leaving only the appropriate fuse for the bad address from the input of four signals, RC0 to RC3. In case of DT, one signal output through this selected fuse is left from the input of four signals RD0 to RD3. to be.

In FIG. 1 (a), ABT and CDT are signals for ultimately generating a signal for controlling a redundancy decoder or a normal decoder, and ABT is a NAND through NAND gate 4 that uses the above-mentioned AT and BT signals as inputs. It is an output signal calculated with logic, and CDT is an output signal calculated with NAND logic through NAND gate 5 which takes in the above-mentioned CT and DT signals. In Fig. 1 (a), ∮Ri (i = 1, 2, 3, 4 in Fig. 1) is a signal for controlling the redundancy decoder or the normal decoder with the output through the redundancy predecoder, and ∮R1 is mentioned above. ABT and CDT are computed through Noah Gate 6.

The operation of FIG. 1 (a) will be described with reference to FIG. 1 (b). When no defective cells are generated in the normal memory cell array, all the fuses of FIG. 1A are not cut. In addition, each passgate is " turned off " so that one input of the first and second NAND gates 4 and 5 is both " low " by the enable fuses MF3 and MF4. Then, the first and second NAND gates 4 and 5 output the ABT and CDT signals in the "high" state, respectively, and the NOR gate 6, which is the output terminal, is " Rl " 0,1,2,3,4) will be output. The " Ri " state of the " Ri " signal enables the normal decoder and disables the redundant decoder. (The reason is that the " R " rI signal of the " low " state only enables the normal decoder. Since the logic (1ogic) of the decoder can be arbitrarily determined according to the ∮Rl signal, it can be easily understood by those skilled in the art, for example, even when the iRi signal is output in a "high" state. Each decoder can be designed to enable a normal decoder and to disable the redundant decoder).

On the other hand, when a defective cell is generated in the normal memory cell array, all of the enable fuses MF1 to MF4 are cut to enable the repair operation. Each of the pass gates G1 to G16 is " turned on " to transmit an input address, and among the fuses F1 to F16, all fuses other than the fuse connected to the address to be decoded are cut and decoded. Only an address (i.e., an address that designates a predetermined generated bad cell) is outputted, i.e. to decode the addresses of A0, B0, C0, D0 and repair the cells corresponding to these addresses. Except for the fuses F1, F5, F9, and F13, all other fuses must be cut (i.e., 16 including the fuses MF1 to MF4), and as shown in FIG. AT, BT, CT, and DT are generated as signals of a `` high '' state, and the ABT and CDT are signals of a `` low '' state, respectively, so that the noar gate 6 of the output terminal is in a "high" state. Ri signal is output. From this it will be readily seen that the normal decoder is disabled and the redundant decoder is enabled. However, in the circuit illustrated in FIG. 1A, when decoding a predetermined address during a repair operation, all other than the fuse connected to the address to be decoded must be cut. This causes an inefficiency of cutting 16 fuses to input four address signals as in the above case. This also results in the repair operation not being performed if the fuse to be cut is not cut, thereby reducing the reliability of the redundancy function.

Accordingly, an object of the present invention is to provide a semiconductor memory device in which the efficiency of the redundancy operation is improved by minimizing the fuse to be cut in the repair circuit during the redundancy operation.

In order to achieve the object of the present invention, the present invention provides a normal memory cell array in which predetermined data is stored, and a normal decoder unit for inputting an external address signal to store a predetermined selected memory cell in the normal memory cell array. And specifying a redundant memory cell array in which the defective memory cells are stored in the normal memory cell array when the defective cells are generated, and a predetermined replacement memory cell in the redundant memory cell array by inputting the external address signal. A redundant decoder unit for inputting the external address and an output connected to one of the normal decoder unit and the redundant decoder unit, respectively, to enable only a predetermined first output unit and the normal decoder unit to perform the redundant operation at a predetermined second output. A repair circuit for enabling only the decoder unit A semiconductor memory device having: an input terminal having each of the different external addresses as one input and each output of a plurality of fuse circuits as a type force; and having an address of a predetermined memory cell to be repaired during a repair operation. It is characterized in that the repair circuit for performing the repair operation by cutting only the fuse of the fuse circuit coming in the type of the predetermined one input circuit input. Each of the fuse circuits is a circuit in which a fuse and a resistance element are connected in series between a power supply voltage terminal and a ground voltage terminal, and a common terminal thereof is an output node.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Prior to the description, it should be noted that the repair circuit according to the present invention disables and enables the normal decoder and the redundant decoder by cutting only a fuse circuit that is a type of one input circuit for inputting an address to decode during a repair operation. . In addition, AT, BT, CT, DT, ABT, CDT, and "Ri," Rj used in FIGS. 2 and 3 are mentioned in the above description of FIG. 1 and the meanings described above in the following description. Note that it is used as.

2 and 3 show a repair circuit according to the present invention. 2 is configured to output an address through a noar gate as a first embodiment, and FIG. 3 is configured to output an address through a NAND gate as a second embodiment. 2 and 3 show only a repair circuit in a semiconductor memory device as shown in FIG. 1 of the prior art, and it is clear that the dotted line block is a repair circuit according to the present invention.

FIG. 2 (a) is one embodiment of the repair circuit according to the present invention, and the operation timing thereof is the second diagram (B). The structure of the said FIG. 2 (a) is demonstrated. The configuration of FIG. 2A includes a normal memory cell array in which predetermined data is stored, a normal decoder unit for inputting an external address signal to designate a predetermined selected memory cell in the normal memory cell array; A redundant memory cell array in which cells for replacing defective cells in the normal memory cell array are stored, and a redundant decoder for designating predetermined replacement memory cells in the redundant memory cell array by inputting the external address signal. In a semiconductor memory device having a negative portion, a plurality of input stages (11) (12) (...) each having the different external addresses as one input and each output of the plurality of fuse circuits as a type force, and the respective input stages (11) (12) A plurality of transmission stages 13 ... Songdan 13 is made of a repair circuit output terminal 14 to be connected (‥) each being output is the input of the output is respectively connected to one input the normal decoder and the redundant decoder portion. In the above configuration, only the fuse circuits connected to RA0 and RA1 are shown, and the noah gate of the transmission stage also shows only the noah gate 13 that outputs the AT signal.

In addition, it is noted that each of the resistors RR1, RR2, ... connected to the ground voltage terminal in each fuse circuit is a high resistance element. Referring to the configuration of FIG. 2 (a), although not shown, a noah gate is provided as an input terminal for outputting A2 'and A3', and a noah gate as a transmission terminal for outputting BT, CT and DT is further provided. Can understand.

Based on the structure of FIG. 2 (a), the operating characteristics will be described with reference to FIG. 2 (B). When no defective cells are generated in the normal memory cell array, the fuses RFl, RF2, ... are not cut. Therefore, the noar gates 11 (12) (...) of the input terminal are A0 ', A1', ... in the "low" state. The signal is output, and the NOA gate 13 (...) of the transmission end outputs the AT, BT, CT, and DT signals in the "high" state. From this, the NOR gate 14 of the output stage outputs the R1 signal in the "low" state, and the R1 signal in the "low" state enables the normal decoder through the NOA gate 21 and at the same time the delay circuit ( 22) disable the redundant decoder. Then, when a bad cell occurs in the normal memory cell array, for example, if the addresses to be decoded are RA0, RB0, RC0, and RD0, only the fuse RF1 that forms the input of the noar gate 11 of the input terminal is the same as the RA0 signal. For example, cut using the same method as the laser projection method. Then, as can be seen in FIG. 2 (B), the NOA gate 11 of the input terminal outputs the "high" A0 'signal. (A1, A2', and A3 'signals are connected to each input terminal. Since the fuse RF2 (…) is not cut, it is continuously output as a signal of the "low" state). Then, the NOA gate 13 of the transmission stage outputs the AT signal of the "low" state by A0 'of the "high" state. (In this case, the BT, CT, and DT signals are also output as "low" signals). Therefore, the output signal #Ri of the NOR gate 14 of the output terminal is output in a "high" state to disable the normal decoder and enable the redundant decoder. From this, a predetermined selection of the memory cell to be replaced is made. As can be seen from the above description, in the repair circuit according to the present invention, the repair operation is performed more efficiently by cutting only the fuse circuit (that is, the number of addresses to be decoded) that enters the same input as the address to be decoded.

In the circuit of FIG. 3A, each NOR gate of FIG. 2A is implemented as a NAND gate. In addition, according to the NAND gate, a resistor circuit is connected to a power supply voltage terminal and a fuse is connected to a ground voltage terminal. The operation characteristic of FIG. 3A will be described with reference to FIG. 3B. When the repair operation is not performed, the fuse circuit input of the NAND gates 31 (32) (...) at the input terminal is " low " and the NAND gates 31 (32) (...) are disabled and the " high " A0 ', A1',... Output the signal. The NAND gate 33 (...) of the transmission stage outputs the AT, BT, CT, and DT signals in the "low" state, and the NAND gate 34 of the output stage outputs the R1 signal in the "high" state. From this the normal decoder is enabled and the redundant decoder is disabled. On the other hand, when a repair operation occurs, for example, if the addresses to be decoded are RA0, RB0, RC0, and RD0, the fuse RF1 of the fuse circuit for one input of the NAND gate 31 of the input terminal to which the RA0 signal is input is cut. do. Then, as shown in FIG. 3 (b), the NAND gate 31 of the input terminal outputs the A0 'signal in the "low" state (A1', A2 ', and A3' signals of the input terminal continue to be "high". The NAND gate 33 of the transmission stage outputs the AT signal in the "high" state (similarly, the BT, CT, and DT are also output in the "high" state). From this, the #Ri signal is output in a "low" state, disabling the normal decoder and enabling the redundant decoder. As described above, the repair operation is performed in the state in which only fuses corresponding to the number of addresses to be decoded are cut. As shown in FIGS. 2 and 3, in the prior art, the repair operation is performed by cutting everything except the fuse connected to the address to be decoded, thereby greatly reducing the efficiency. However, in the present invention, the fuse is cut only by the number of addresses to be decoded. This increases the efficiency.

The circuits of FIGS. 2 and 3 are optimal embodiments of the present invention, and a method of transmitting an address to be decoded from an input terminal to an output terminal, for example, logic, etc. without departing from the technical spirit of the present invention. Those skilled in the art will understand that it may be configured differently, such as by using other logic gates in consideration of the above.

As described above, in the present invention, the repair circuit cuts and transmits the output of the input terminal, an output terminal of which an external address and a fuse circuit are input to the repair circuit so as to cut only fuses as many as the number of addresses to be coated, and an output of the transmission terminal. A signal for enabling or disabling the normal decoder and the redundant decoder by inputting the input signal is configured as an output terminal for outputting the cut circuit. The fuse circuit is a type force of a one input circuit to which an address to be decoded is input during a repair operation. The semiconductor memory device can improve the efficiency of the redundancy operation by efficiently performing the repair operation by changing only the output state.

Claims (7)

A normal memory cell array in which predetermined data is stored, a normal decoder unit for inputting an external address signal to store a predetermined selected memory cell in the normal memory cell array, and when a defective cell occurs in the normal memory cell array A redundant memory cell array in which the repaired memory cell is stored, a redundant decoder unit for inputting the external address signal to designate a predetermined repair memory cell in the redundant memory cell array, and inputting and outputting the external address A semiconductor memory device having a repair circuit connected to one input of the normal decoder unit and the redundant decoder unit to enable only the normal decoder unit during a normal operation and to enable only the redundant decoder unit during a repair operation. An input terminal having an external address as one input and a type force corresponding to each output of the plurality of fuses, respectively, a plurality of transmission terminals having outputs of each input terminal connected to one input, and an output of each transmission terminal A type force of a predetermined one input circuit having an output terminal connected to each input and an output connected to one input of the normal decoder unit and the redundant decoder unit, respectively, wherein an address of a predetermined memory cell to be repaired is input during the repair operation. The repair circuit, characterized in that for performing the repair operation by cutting only the fuse of the fuse circuit. The repair circuit according to claim 1, wherein each of the fuse circuits is a circuit in which a fuse and a resistor are connected in series between a power supply voltage terminal and a ground voltage terminal, and a common terminal thereof is an output node. A normal memory cell array in which predetermined data is stored, a normal decoder section for inputting an external address signal to designate a predetermined selected memory cell in the normal memory cell array, and when a defective cell occurs in the normal memory cell array 10. A semiconductor memory device having a redundant memory cell array in which a cell for replacing is stored, and a redundant decoder unit for inputting the external address signal to designate a predetermined memory cell in the redundant memory cell array. A plurality of input terminals each having an external address as an input and each output of the plurality of fuse circuits as a type force, a plurality of transmission terminals to which the outputs of the input terminals are connected as one input, and the outputs of the respective transmission terminals Connected by one input and the output is Semiconductor memory device characterized by comprising a repair circuit of the output stage are connected respectively to far the decoder unit and the input redundant decoder portion. 4. The semiconductor memory device according to claim 3, wherein the input terminal, the transmission terminal, and the output terminal each comprise a NOR circuit. 4. The semiconductor memory device according to claim 3, wherein the input terminal, the transmission terminal, and the output terminal are each formed of a NAND circuit. 4. The method of claim 3, wherein the repair circuit cuts only a fuse circuit that becomes a type force of one input circuit for inputting an address to decode during a first predetermined operation, thereby disabling and enabling the normal decoder and the redundant decoder, respectively. And a semiconductor memory device characterized by the above-mentioned. 7. The semiconductor memory device of claim 6, wherein the first operation is a repair operation for selecting a replacement memory cell in the redundant memory cell when performing a redundancy function.