KR940006742B1 - Testing apparatus for isdn subscriber testing - Google Patents

Abstract

The test apparatus comprises a TD-bus for transmitting data necessary for switching, a waveform generator for transmitting and receiving an address signal decoded from the TD-bus, a waveform shaper for receiving an output signal of the waveform generator and transmitting a read control signal to the TD-bus, a waveform transformer for receiving a clock signal and generating a control signal, and a switching device for switching a B channel from a subscriber and transmitting data to be sent to a peripheral processor to the TD-bus, thereby effectively implementing a test.

Description

Test equipment for testing ISDN subscribers

1 is a block diagram of the present invention.

2 is a circuit diagram of the present invention.

3 is a waveform diagram at the time of reading.

* Explanation of symbols for the main parts of the drawings

101: TD-bus section 102: waveform generator

103: MT8980 switch element portion 104: waveform deformation portion

105: waveform shaping unit

The present invention relates to a test apparatus for testing ISDN subscribers.

The present invention is a test device for the digital subscriber matching device of the TDX-10 electronic switchboard, and implements a T switch function for testing a system including a basic speed (2B + D), a primary group speed (30B + D) subscriber and a terminal. The purpose of this function is to provide a test apparatus (ISTA) for effectively performing the systemic tests required for digital subscribers that match the exchange.

The basic speed subscriber matching device of the TDX-10 ISDN exchange processes layer 1 in the subscriber matching board and layer 2 in the D-channel processing board (IDPA). The B and D channels are separated in the subscriber matching board, and the D channel is switched by IDPA and the B channel by PCM cable. The test apparatus of the present invention (ISTA) is connected to the IDPA and PCM cable on one back board (PBA) acts as a B-channel switch for the system test, and is connected to the peripheral processor (PP) and TD-bus cable switching Implemented to receive control for

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall configuration diagram of the present invention, where 101 denotes a TD-bus portion, 102 denotes a waveform generating portion, 103 denotes an MT8980 switch element portion, 104 denotes a waveform deformation portion, and 105 denotes a waveform forming portion.

The MT8980 switch element unit 103 transmits information necessary for switching by using the address decoded by the TD bus unit 101, the Naita bus, RDY (Ready), PCLK, and -PCLK (system clock) from the PP (peripheral processor). It is a circuit that can be written to and read from.

In order to switch the B channel (RX 0-3) received from the subscriber (RX 0-3), it is exchanged using the MT8980 switch element unit 103, and then data is transferred to the B channel connected to the subscriber (TX 0-3). A circuit exchange is performed for transmission of data within or between subscriber boards of a subscriber block.

The operation of the MT8980 switch element unit 103 will be described in more detail as follows.

After designating the common memory (-Low) of the control register, specifying the stream (STI0-STI7), and writing the switching information to the common memory (-Low) by specifying the channel as A0-A5, the common memory (- MT8980 access is completed after the output of the corresponding channel is enabled at the same time as the switching mode at high), and afterwards, the MT8980 sends the data input to the designated channel of the designated stream to the designated stream (STO0-). The output data is loaded on the designated channel of STO7), and the switching operation is performed as desired in the system test. The waveform generating unit 102, the shaping unit 105, and the deforming unit 104 will be described in detail with reference to FIG. 2.

The necessary data for the switching operation described above is written in a register, and as a logic circuit as shown in FIGS. 1 and 2 so that the corresponding address can be designated and the data can be controlled through the TD bus from the PP (ISAP). In case of writing data, after several clock (MCLK) time has passed on the TD-bus, it should be accessed through the data bus at the corresponding address of the register of MT8980. In order to operate MT8980, MTCS *, DTACK ·, MCLK *, Signals such as FOI *, DS, C4I *, and WR are required, and as described above, this is implemented by logic design, and it operates separately when writing and reading. This is to operate according to TD-bus. Is as follows.

2 is a detailed circuit diagram of the present invention.

The TD-bus is a known bus that is configured to multiplex signals from a PP (a peripheral processor), enter them in series, and convert them in parallel to produce various signals. In the figure, A0-A5 represents the decoded address on the TD-bus, D0-A7 represents the decoded databus and is used to control the MT8980.

The signal flow between the TD-bus section 101 and the waveform generator section 102 is necessary to control the MT8980 element of the switch element section 103, but when writing data to the MT8980 via the TD bus, it is possible to write -WRP (Write; operation). When low) and -RDP (Read: low when operating) is designed to operate separately because the operation is different, and the case that the waveform shaping unit 105 necessary for this is a read and write The waveform is generated by the DS8980 switch element. DS, MTCS * (operation low) is generated to operate the MT8980 switch element, and the corresponding address and data are replaced in advance. Where DS is the MT8980's data strobe signal, MTCS * is the MT8980's chip select signal, and when accessed, it is operating low.

On the other hand, after writing, the operation does not change while reading or continuing to supply power (SV) until the MT8980 switch element is accessed again and written.

If the programmer or engineer needs to read which state the MT8980 switch element is in, the read operation is possible. In this case, the waveform shaping section 105 delays -RDP and DTACK * (operation low) by about 100 ns. -Create a DS signal using RDY (TD-bus signal as an operating low) and another signal as a trigger signal, and create an MTCS * (operating low) signal at approximately the same time, and clock (FSBR, MCLK) at waveform transform 104. By inputting the signals made by changing the signal to the MT8980, the corresponding data is loaded on the data line (D0-D7), and this data is connected to the TD-bus unit 101 so that the data can be transferred to the PP. In the waveform generator 102, -RDY controls U16, shaping -RDY to control U16 simultaneously by combining with -RDY, and controlling U9 by combining DTACK * and -RDP. Is done It was configured to. In the figure, the FS signal is not a TD bus signal and is used to transmit and receive data to and from the subscriber board while operating the MT8980.

As shown in FIG. 3, when writing, MTCS *, -WRP is low, and DS is high (5V) after several clocks (MCLK) time has elapsed since data was written after the TD-bus RDY signal. Should receive DTACK * and complete the write operation.

When reading, the DTACK * is first received from PP and the reading operation (control signals such as MTCS *, MCLK, FOI *, DS, C4I *, WR, etc. are operated in MT8980) is made and then several clocks (MCLK) time elapses. Accurate data (D0-E7) is stored in the latch so that it can be read from the PP after a parallel-to-serial conversion to TD-bus specifications.

2B data from subscriber is connected to 4 subhighways to send and receive data, and TTL Logic is a circuit that acts as a T-SW to provide the necessary clocks (FS, MCLK) to T-SW (Time Switch). It converts 8KHz, 4MHz clock into differential signal and provides it to the subscriber board to serve as an interface, while accepting C4I * as an input clock in U26 of FIG. 2 and receiving FOI * signal through U26, LS164, U27, and LS00. It is a circuit designed to operate the MT8980.

It is designed to control the information necessary for switching through the TD-bus by executing the system test program embedded in the F / W by using the MMC port mounted in PP (ISAP) by configuring the circuit as above. .

In order to implement this system test function, subscriber matching board for processing Layer 1 including subscriber line and digital communication, IDPA for interaction between other blocks such as Layer 2 processing related to D-channel protocol, and supply power for these boards It consists of a power supply unit, ISDN test Jig Board Assembly (ISA) that can act as a T-SW in ISDN terminal and system, PP for controlling ISTA, and various back boards. On the other hand, the connection with other blocks (PP, subscriber) is transmitted / received by the reliable RS-422 method (Differential Line Driver, Receiver).

The effect obtained by the present invention is performed at the system level by connecting the lSDN terminal and the TDX-l0 system composed of the primary and primary group access digital subscriber registration boards performing the layer 1 functions, lDPA, and PP (ISAP). The test can be easily performed similarly to the system environment without a T-SW block consisting of more than 10 PBAs and PP (TSP), so that the test can be easily performed, cost-saving, maintenance function, and multiple Effective tests could be conducted in conducting terminal tests and functional tests.

ISTA designed the circuit so that the test environment could be established regardless of the circuit code and version of the TDX-10 subscriber board. After fabricating the ISTA, ISTA could effectively perform the system test and the interworking test of each PBA.

Claims (1)

A test apparatus for testing a system including a primary and primary group access digital subscriber registration board performing a layer 1 function, an electronic exchange consisting of a D-channel processing board and a peripheral processor (PP) and an ISDN terminal connected to the exchange, A TD bus unit 101 for transmitting information necessary for switching from the peripheral processor PP, a waveform generator 102 connected to the TD bus for transmitting and receiving an address signal decoded from the TD bus, A waveform shaping unit 105 connected to the TD-bus and the waveform generator 102 to input an output signal RDY from the waveform generator 102 to output a read control signal to the TD-bus; A waveform modifying unit 104 for inputting a clock signal to generate a control signal, and connected to the respective elements to control the waveform generating unit 102, the waveform shaping unit 105, and the waveform modifying unit 104. God And an MT8980 switch element unit (103) for switching the B channel from the subscriber by inputting calls and sending the information to the peripheral processor to the TD-bus unit (101).