KR940006658B1 - Semiconductor memory device and fabricating method thereof - Google Patents

Abstract

The data of a bit line is stored on a capacitor and the capacitor voltage is used as input voltage of a sense amplifier so that the stored data is not altered. The method comprises the steps of: (A) forming a first and a second gate electrode on a substrate (10); (B) forming a first to a third diffusion area beside the gate region; (C) removing the gate insulating layer except a first and a second gate electrode; (D) forming bit line between a first and a second electrode and a second diffusion area; (E) spraying insulating material on the electrodes and grooving the insulating material to form a contact hole; (F) forming capacitor first electrode and (G) forming dielectric layer on the capacitor first electrode and forming a capacitor second electrode.

Description

Semiconductor memory device and manufacturing method

1 is a circuit diagram of a memory device composed of one transistor and one capacitor of the prior art.

2 is an equivalent circuit diagram of a memory device of the present invention.

3 is a cross-sectional view of a semiconductor memory device according to one embodiment of the present invention.

4 is a diagram for explaining a process of manufacturing a semiconductor memory device according to one embodiment of the present invention;

* Explanation of symbols for main parts of the drawings

Ml, M2, M3: MIS transistor 10: Semiconductor substrate

C1, C2: Capacitor 30,31: Gate insulating film

BL: Bit line 40, 50, 60: Diffusion area

WW: Recording word line 70, 80, 90: conductive layer

WR: Reading word line 120, 140, 160: conductive layer

Vref: reference voltage line 100: insulating film

130: dielectric film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device (memory cell) capable of storing binary and multi-digital numbers, and in particular, configured to read stored information without breaking the charge state of charge of the capacitor storing the information. A semiconductor memory device and a method of manufacturing the same.

A dynamic random access memory (DRAM) cell widely used as a conventional semiconductor memory device has an equivalent circuit as shown in FIG. 1, and the information in the bit line BL ("1" or "0") at the time of writing. Is written as the amount of charge in capacitor C1 designated by word line WL (BL and C1 are connected by conduction of M1), and at reading is stored in information " 1 " or " 0 " stored in capacitor C1 designated by word line WL. The corresponding charge amount) is transferred to and read from the bit line BL due to the conduction of the switching element M1.

In the memory device having such a structure, when the information of the stored logic value is read out, only a very slight voltage change occurs in the bit line when the capacitor C1 is much smaller than C2. That is, when the logic value "l" (high voltage) is stored in the capacitor C1, the potential of the bit line rises slightly, and when the logic value "0" (zero voltage) is stored, the voltage of the bit line decreases slightly. The sense amplifier connected to the bit line then detects this minute voltage change and reads an information value of "1" or "0". In the conventional memory device, there is a limit on the voltage that the sense amplifier can discriminate. However, since a large number of information memory devices are required to be input in a limited semiconductor area, it is necessary to satisfy these two opposing requirements. It was virtually impossible.

An object of the present invention is to store the information of the bit line in the capacitor C1 and use the voltage stored in this C1 as the input voltage of the amplifier without changing the stored information so that the voltage of the bit line is changed so that the stored information can be read. As a memory device, there is provided a semiconductor memory device capable of storing multiple values of information including a bit line, a write word line, and a read word line.

The semiconductor memory device of the present invention includes the semiconductor substrate 10, the first, second and third diffusion regions 40, 50, 60, first and second diffusions formed at predetermined intervals on the surface portion of the semiconductor substrate, respectively. The first conductive layer 70 provided with the insulating layer 30 interposed on the predetermined interval between the regions, and the second provided with the insulating layer 31 interposed on the predetermined interval between the second and third diffusion regions. The conductive layer 80, the third conductive layer 90 connected to the second diffusion region, the fourth conductive layer 120 electrically connecting the first conductive layer and the third diffusion region, the fourth conductive layer and the dielectric film. A first MIS transistor comprising a fifth conductive layer 140 interposed between the first and second diffusion regions 160, the first and second diffusion regions and the first conductive layer And a second MIS transistor including the second and third diffusion regions and the second conductive layer, and a capacitor for storing charge between the fourth conductive layer and the fifth conductive layer. As the dielectric layer 130 used in the capacitor, an oxynitride layer (Oxy-Nitride) in which an oxide layer (SiO 2) and a nitride layer (Si 3 N 4) are stacked in multiple layers is used.

4 is a cross-sectional view for explaining a manufacturing process of a semiconductor memory device according to one embodiment of the present invention. As shown in FIG. 4A, after the field oxide film 20 is grown on the semiconductor substrate 10, the gate insulating film and the polysilicon layer are formed to form the first and second gate electrodes. Next, as shown in FIG. 4B, ions are implanted into the semiconductor substrate around the gate to form first, second, and third diffusion regions 40, 50, and 60.

Thereafter, gate insulating films other than the first and second gate portions are removed, and then a bit line 90 is formed between the first and second gate electrodes and on the second diffusion region 50 (FIG. 4C). After the insulating material is coated thereon, the insulating material is etched to form contact holes in the first gate electrode and the first and third diffusion regions (FIG. 4D).

Subsequently, a capacitor first electrode is applied to electrically connect the reference voltage line 160 connected to the first diffusion region, the third diffusion region 60 and the first gate electrode 70 by applying a conductive material. 120 is formed (FIG. 4E). Subsequently, after forming the dielectric film 130 on the capacitor first electrode, the capacitor second electrode 140 is formed (FIG. 4f).

Thereafter, a metal wire protective film 150 coating process, which is generally performed in a semiconductor manufacturing process, is performed.

The operation of the present invention formed as described above will be described with reference to FIG. 2 equivalent circuit.

The first diffusion region, the second diffusion region, and the first conductive layer constitute one MIS-FET, that is, M2.

In addition, the second diffusion region, the third diffusion region and the second conductive layer constitute another MIS-FET, that is, M3. The fourth conductive layer and the fifth conductive layer form a capacitor C1 with a dielectric film interposed therebetween.

The third conductive layer is used as a bit line, the sixth conductive layer is used as a reference voltage line, the second conductive layer is used as a write word line, and the first conductive layer is used as a read word line. The equivalent circuit of the semiconductor memory device of FIG. 3 is FIG. 2, and the semiconductor memory device of FIG. 3 embodies the electronic circuit of FIG.

In the operation of the memory device configured as described above, the write instruction signal is applied to the write word line WW to the information proxy so that M2 is "on" and the information of the bit line BL is stored in the capacitor C1. At the time, when a predetermined voltage, which is a read command signal, is applied to the read word line WR, it is added to the potential held at the capacitor C1 and applied to the gate of M3, and the voltage of the reference voltage line changes according to the magnitude of the gate voltage. The bit line BL is displayed on the bit line BL to detect the voltage of the bit line and to read the stored information. M3 operates as an amplifier or an amplification switch.

In the semiconductor memory device, since the charge stored in the capacitor C1 is not destroyed and only the potential thereof is used for reading, the capacitor of the large capacity is not required, and the memory capacity of the memory device can be greatly increased. Hexadecimal, hexadecimal, etc. can be stored in one cell, which can be very useful.

Claims (3)

Semiconductor substrates; First, second and third diffusion regions formed on the surface portion of the semiconductor substrate at predetermined intervals, respectively; A first conductive layer provided with an insulating layer interposed therebetween at a predetermined interval between the first and second diffusion regions; A second conductive layer provided with an insulating layer interposed therebetween at a predetermined interval between the second and third diffusion regions; A third conductive layer connected to the second diffusion region; A fourth conductive layer electrically connecting the first conductive layer and the third diffusion region; A fifth conductive layer provided with the fourth conductive layer and a dielectric film interposed therebetween; A sixth conductive layer connected to the first diffusion region; A first MIS transistor comprising the first and second diffusion regions and the first conductive layer; A second MIS transistor including the second and third diffusion regions and the second conductive layer; And a capacitor for storing charge between the fourth conductive layer and the fifth conductive layer. The semiconductor device of claim 1, wherein the first, second, and third diffusion regions have a conductivity type opposite to that of the semiconductor substrate, and the first to sixth conductive layers are formed of polysilicon, and the fourth conductive layer and the fifth conductive layer. A semiconductor memory device characterized in that the dielectric film therebetween is an industry-academia nitride film. A method for manufacturing a semiconductor memory device, comprising: forming a gate insulating film and a polysilicon layer on a semiconductor substrate to form first and second gate electrodes, and then forming first, second, and first electrodes in a semiconductor substrate around the gate electrode. A diffusion region is formed; Removing a gate insulating film other than the first and second gate electrode portions, and forming a bit line between the first and second gate electrodes and over the second diffusion region; After the insulating material is coated on the electrodes, the insulating material is etched to form contact holes in the first gate electrode and the first and third diffusion regions, and a conductive material is applied thereon, thereby performing the photolithography process. A capacitor first electrode for electrically connecting the reference voltage line connected to the first diffusion region, the third diffusion region, and the first gate electrode to each other; And forming a capacitor second electrode after forming a dielectric film on said capacitor first electrode.