JPH02309668A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To accelerate the reading-out operation in the stable state by a method wherein the first cell plate electrodes are formed on the above parts of source parts as the first charge accumulation parts likewise the second cell plate electrodes are formed on the above parts of the second accumulation parts. CONSTITUTION:The second charge accumulation parts 7 connected to the first charge accumulation parts 6 are formed on the above parts of the first cell plate electrodes 6; while the first cell plate electrodes 8 are formed on the above parts of source parts 2 as the first charge accumulation parts 6; furthermore, the second cell plate electrodes 9 are formed on the above parts of the second charge accumulation parts 7. Thus, the first and second charge accumulation parts 6, 7 for memory are formed on the surface and above parts of a semiconductor substrate 1 so that the capacitance of memory cell may be increased without increasing the space of the same. Through these procedures, the reading-out operation can be accelerated without performing any erroneous operation at all during the signal reading-out process.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor memory device.

2. Description of the Related Art Recently, the density of semiconductor memory devices has increased, and in particular, the integration and density of dynamic random access memories (DRAMs) have been remarkable. The development of semiconductor memory devices is largely due to the memory cell structure, which occupies more than half of the chip size. A conventional semiconductor memory device will be explained with reference to FIGS. 3 and 4. In FIGS. 3 and 4, 31 is a semiconductor/body substrate, to the surface of which are connected a source part 32 that constitutes a MOS type transistor for switching when reading and writing signals, and a conductor 33 as a bit line. drain section 34,
A gate electrode 35 as a word line is formed, and a charge storage section 3 as a memory cell is formed above the source section 32.
6 and a cell plate electrode 37 are formed. In addition, 38 is a gate oxide film, 39 is an insulating film for forming a memory capacitor, 40 is an insulating film for cell isolation, and 41 is an insulating film for forming a memory capacitor.
42 is a contact window that connects the conductor 33 and the drain portion 34, and 42 is a contact window that connects the charge storage portion 36 and the source portion 32.

The above configuration is a so-called stacked memory. This memory cell stores information or signals from the bit line in the charge storage section 36 through the drain section 34 and source section 32 by setting the logic voltage of the gate electrode 35 constituting the word line to "H". A signal stored in the charge storage section 36 is written into the charge storage section 36 and read out from the source section 32 and the drain section 34 to the bit line.

Problem to be Solved by the Invention By the way, according to the above configuration, the charge storage section 3 for memory
6 is formed only above the semiconductor substrate 31, so if the area of the memory cell is made smaller for higher density, the capacity of the memory cell will be smaller, making it more likely to cause malfunctions during signal readout, thus increasing the readout speed. The problem was that it became difficult.

Therefore, an object of the present invention is to provide a semiconductor memory device that can solve the above problems.

Means for Solving the Problems In order to solve the above problems, the semiconductor memory device of the present invention has an M for switching when reading and writing signals on the surface of the semiconductor substrate.
Forming a source part constituting an OS type transistor, a drain part to which a conductor as a bit line is connected, and a gate electrode as a word line, and making a part of the source part a first charge storage part, A second charge storage section connected to the first charge storage section is formed above the first charge storage section, and a first cell plate electrode is formed above the source section which is the first charge storage section. , and a second cell plate electrode is formed above the second charge storage section.

According to the above structure, the first and second charge storage parts for memory are formed on the surface of the semiconductor substrate and the upper part of the semiconductor substrate, so the capacity of the memory cell can be increased without increasing the area of the memory cell. can do.

EXAMPLE An example of the present invention will be described below with reference to FIGS. 1 and 2.

Reference numeral 1 denotes a semiconductor substrate of one conductivity type, and its surface portion includes a source portion 2 constituting a MOS type transistor for switching when reading and writing signals, a drain portion 4 to which a conductor 3 as a bit line is connected, and a word line as a word line. A gate electrode 5 is formed. Note that the source section 2 and drain section 4 are of the opposite conductivity type to that of the semiconductor substrate 1. and,
A part of the source section 2 is made into a first charge storage section 6, and above the first charge storage section 6 is a second charge storage section connected to the first charge storage section 6. 7 is formed. Further, a first cell plate electrode 8 is formed above the source portion 2 which is the first charge storage portion 6, that is, between the first charge storage portion 6 and the second charge storage portion 7. At the same time, a second charge storage section 7 is provided above the second charge storage section 7.
A cell plate electrode 9 is formed.

Note that the gate electrode 5 is disposed within the gate oxide film 10, and between the first charge storage section 6 and the first cell plate electrode 8, and between the first cell plate electrode 8 and the second charge storage section. 7 and between the second charge storage section 7 and the second cell plate electrode 9, there are first, second and third insulating films 11, 12.1, respectively, constituting a memory capacitor.
3 is formed. Further, since the first cell plate electrode 8 is disposed between the two types of load accumulation parts 6 and 7, it acts on both types of load accumulation parts 6 and 7. Furthermore, 14 is an insulating film for cell isolation, 15 is a contact window that connects the conductor 3 as a bit line and the drain part 4, and 16 is a contact window that connects the first and second charge storage parts 6, 7 and the source part 2. This is a contact window for connection.

In the above configuration, by setting the logic voltage of the gate electrode 5 constituting the word line to "H", information or signals from the bit line are passed through the drain section 4 and the source section 2 to the first and second charge storage sections 6. , 7, and the signals accumulated in the first and second charge storage sections 6, 7 can be read out from the source section 2 and drain section 4 to the bit line.

In this way, the first and second charge storage portions 6.
7 is formed on the surface portion of the semiconductor substrate 1 and the upper portion of the semiconductor substrate 1, the capacity of the memory cell can be increased without increasing the area of the memory cell.

Effects of the Invention As described above, according to the structure of the present invention, since the first and second charge storage parts for memory are formed on the surface part of the semiconductor substrate and the upper part of the semiconductor substrate, it is possible to increase the area of the memory cell. Therefore, the capacity of the memory cell can be increased, and the read operation can be performed at high speed in a stable state.

[Brief explanation of drawings]

FIG. 1 is a plan view of a main part of an embodiment of a semiconductor memory device of the present invention, FIG. 2 is a sectional view taken along the line II in FIG. 1, FIG. 3 is a plan view of a main part of a conventional example, and FIG. It is a sectional view taken along the line ■-■ in FIG. 3. 1... Semiconductor substrate, 2... Source part, 4...
・Drain part, 5...gate electrode, 6...first
charge storage section, 7... second charge storage section, 8...
- First cell plate electrode, 9... second cell plate electrode. Figure 3 11”

Claims (1)

[Claims] 1. A source part constituting a MOS type transistor for switching when reading and writing signals, a drain part to which a conductor as a bit line is connected, and a gate electrode as a word line are formed on the surface part of the semiconductor substrate, and the above-mentioned A part of the source part is used as a first charge storage part, and a second charge storage part connected to the first charge storage part is formed above the first charge storage part, and the second charge storage part is connected to the first charge storage part. A semiconductor memory device in which a first cell plate electrode is formed above a source portion which is a charge storage portion, and a second cell plate electrode is formed above the second charge storage portion.