KR940006458Y1 - Output buffer circuit of semiconductor memory device - Google Patents

Abstract

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Description

Output buffer circuit of semiconductor memory device

1 is an output buffer circuit diagram of a conventional semiconductor memory device.

2 is an output buffer circuit diagram of a semiconductor memory device according to the present invention.

3 is an operation timing diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10: VPP Generator 20: Vcc Generator

30: drive circuit 31: load

40: level control circuit 50: load sensing circuit

NM1 ~ MN6: 1st ~ 6th transistor NOR: NOR gate

AND: AND gate INN: inverter

The present invention relates to an output buffer circuit of a semiconductor memory device, and more particularly, to improve speed (SPEED) during data output and reduce the peak current (PEAK CURRENT) during operation to reduce the BOUNCING (BOUNCING) It relates to an output buffer circuit.

In general, the data output buffer of a semiconductor memory has a large capacity load, so the driving force of the buffer must be turned on, which causes a large peak current to flow and the power line bouncing effect, which lowers the driving ability of the buffer. Since it has a swing width of ~ VSS), time is required for outputting data at a predetermined driving capability.

Therefore, the data output buffer of the semiconductor memory device is designed to have high driving capability due to the large load (> = 20pE), and very large peak current is required to output data with high speed. This can cause a bouncing effect on the power level and can have a serious impact on the output performance.

That is, the output buffer circuit of the conventional semiconductor memory device is connected to the reference data line (/ DB) and the Vcc generator 20 which is connected to the comparison data line (DB) to generate the Vcc voltage as shown in FIG. A Vpp generator 10 generating a Vpp voltage higher than the Vcc voltage and the first and second transistors NM1 and NM2 are connected in series and A, which is a connection point between the first and second transistors NM1 and NM2. A load 31 for storing and discharging information is connected to a node, and gate terminals of the first and second transistors NM1 and NM2 are connected to output terminals of the Vpp and Vcc generators 10 and 20 to form a cell. And a drive circuit 30 for charging and discharging the information of 31. The Vpp and Vcc generators 10 and 20 are controlled by an output buffer enable signal OE.

That is, the pair of data lines DB and / DB to be input and the output buffer enable signal are connected to the gate terminals of the first and second transistors NM1 and NM2 of the output drive circuit 30 (VPP-VSS). / (VSS-VCC) is charged / discharged as the load 31, so the swing width of the data output is full-VCC, so the peak current is very large and it is difficult to obtain a fast output. will be.

The present invention utilizes an equalization pracharge (hereinafter referred to as "EQPR") signal to solve the above problems, and adds a level control circuit and a load sensing circuit to maintain a constant level of voltage (VCC to VSS) at all times. (CHARGE) / discharge (DISCHARGE) to be applied quickly to reduce the bounce effect by increasing the speed of data output and reducing the peak current during operation. An output buffer circuit of a semiconductor device comprising a Vpp and Vcc generator for outputting a predetermined voltage by an enable signal, and a drive circuit for charging and discharging a load under control of the generator, wherein the Vpp generator, Vcc generator, and Connected between the drive circuits and the output terminal of the Vpp generator and Vcc generator is assimilated by the EQPR signal. And a load control circuit connected between the output node and the level control circuit for sensing the voltage of the load and operating the level control circuit between the output node and the level control circuit. The present invention provides an output buffer circuit of a semiconductor memory device characterized by being supplied.

Hereinafter, described in detail by the accompanying drawings as follows.

FIG. 2 is an output buffer circuit diagram of a semiconductor memory device according to the present invention, which is connected to a pair of data lines DB // DB and controlled by the output buffer enable signal OE 10. 20) The output terminal is connected to the drive circuit 30 through a level control circuit 40 that operates in accordance with the equalize and precharge signals EQPR. In addition, the contact point A of the drive circuit 30 to which the rod 31 is connected is connected to the level control circuit 40 through a load sensing circuit 50 operated by an opposite signal (/ EQRB) of the equalize precharge signal. It is.

In addition, the level control circuit 40 is a third transistor (NM3) for applying the EQPR signal to the gate and connected to the output terminal of the Vpp generator 10 on one side to control the first transistor (NM1) of the drive circuit (30). And, one end is connected to the output terminal of the Vpp generator 10 and the drain of the third transistor (NM3), the other end is connected to the output terminal of the Vcc generator 20, in parallel between the gates are connected to the load sensing circuit (50) The fourth and fifth transistors NM4 and NM5 for equalizing (equalizing) and precharging the output stages of the Vpp and Vcc generators 10 and 20, and a source terminal connected to an output side of the Vcc generator 20 The stage is composed of a sixth transistor NM6 connected to the output terminal of the load sensing circuit 50 to control the second transistor NM2 of the drive circuit 30.

In addition, the load sensing circuit 50 may include a NOR gate NOR for controlling the sixth transistor NM6 of the level control circuit 40 by combining the output signal of the load 31 and the / EQPR signal, and the / EQPR signal. The AND gate for controlling the fourth and fifth transistors NM4 and NM5 of the level control circuit 40 by combining the inverter INV for inverting the output signal and the output signals of the rod 31 and the inverter INV. AND).

3 is an operation timing diagram according to the present invention.

The present invention made as described above first assumes that the entire state of the load 31 output is " high " (= 3.3 V) and the signal of the data line DB is input to " low " The third transistor NM3 is turned on by the EQPR signal of the pulse.

That is, when the low address strobe (/ RAS) signal goes from "high" to "low" as shown in FIG. 3a, the / OE signal is slightly delayed than the / RAS and falls to "low" before the / OE signal falls to "low". By turning on the third transistor NM3 of the level control circuit 40 by turning the EQPR signal to the "high" level, the third transistor NM3 output terminal is precharged to the appropriate level Vpr-Vtn.

At the same time, in the load sensing circuit 50, the " high " signal of the inverter 31 in which the output of the load 31 in the " high " state and the / EQPR signal in phase opposite to the EQPR signal are inverted at the AND gate AND. Combining the "high" signal outputs the fourth and fifth transistors NM4 and NM5 to turn on to precharge the output of the Vcc generator 20 and equalize the output of the Vpp generator 10.

At this time, the precharge level of the output terminal of the Vpp and Vcc generators 10 and 20 is Vpr-Vtn to turn off the first transistor NM1, which is the drive circuit 30, and turn on the second transistor NM2 to turn on the load ( 31) is discharged through the second transistor NM2.

Therefore, the level of the rod 31 falls to the predetermined level (Vx) as shown in (g), and immediately the output buffer is activated, and the output level of the rod 31 falls to the ground (Vss), and its swing width is Vx. As much as (Vcc), you can get the output faster with less current.

On the other hand, in the opposite case as described above, as shown in (a) of FIGS. 3A and 3B, the entire state of the data output of the load 31 is " low " and the signal / DB of the data field is input as " high ". Suppose that the / EQPR signal, which is the inverted "low" level signal of the EQPR of the short pulse equal to (b), and the outgoing of the load 31 having the "low" level, are noar gates NOR of the load sensing circuit 50. ) Generate a "high" signal, which turns on the sixth transistor MN6 of the level control circuit 40.

Therefore, the output terminal of the Vcc generator 20 is tied in a "low" state, and the Vpp generator 10 turns on the first transistor NM1 of the drive circuit 30 as the output terminal is precharged to a predetermined level (Vpr-Vtn). The Vcc voltage is charged to the load 31 through the first transistor MN1 to raise the potential of the output terminal of the load 31, that is, the A node, to a predetermined level Vy.

Therefore, when the output buffer is operated, the swing width is Vcc-Vy to gain the current and the speed, and the exact level (Vx and Vy level) of the load 31 output stage is set to the pulse width and precharge voltage of the EQPR signal. This can be determined by adjusting the size of (Vpr).

As described above, the present invention synchronizes and precharges the level control circuit 40 and the load sensing circuit 50 with the gate line driving the output stage of the buffer by the EQPR signal. After adjusting the output drive element to preset the output stage of the buffer to a certain potential (between VCC and VSS) in the previous state, charging or discharging to VCC at the preset potential according to the start of driving the data output buffer The predetermined potential may be determined by adjusting the width of the short driving pulse signal or by adjusting the precharge potential of the gate line driving the output terminal of the buffer. Therefore, the output terminal of the load 31 is maintained at a predetermined level (Vx, Vy) to improve the speed of data output during charging and discharging, reducing the peak current during operation, thereby reducing the bouncing of the semiconductor memory device. It can be improved.

Claims (4)

An output buffer circuit of a semiconductor device comprising a Vpp and Vcc generator for outputting a predetermined voltage by an output buffer enable signal, and a drive circuit for charging and discharging a load under control of the generator, wherein the Vpp generator 10 And a level control circuit 40 connected between the Vcc generator 20 and the drive circuit 30 to equalize and precharge the output stages of the Vpp generator and the Vcc generator by the EQPR signal, and the output node 31 and the level. It is composed of a load sensing circuit 50 connected to the control circuit 40 to sense the voltage of the load 31 to operate the level control circuit 40 to charge and discharge the load 31 of a predetermined level An output buffer circuit for a semiconductor memory device, characterized in that a voltage is supplied. The first control circuit of claim 1, wherein the level control circuit 40 has an EQPR signal applied to a gate and connected to an output terminal of the Vpp generator 10 at one side to control the first transistor NM1 of the drive circuit 30. The three transistors NM3 and one end thereof are connected to the output of the Vpp generator 10 and the drain of the third transistor NM3, and the other end thereof are connected to the output of the Vcc generator 20 and are connected in parallel to each other so that the load sensing is possible. A source is provided on the output side of the fourth and fifth transistors NM4 and NM5 for equalizing (equalizing) and precharging the output stages of the Vpp and Vcc generators 10 and 20 by the circuit 50. An output of the semiconductor memory device, characterized in that the stage is connected and the gate stage is connected to the output terminal of the load sensing circuit 50 to control the second transistor NM2 of the drive circuit 30 to control the second transistor NM6. Buffer circuit. The NOR gate of claim 1, wherein the load sensing circuit 50 controls the sixth transistor NM6 of the level control circuit 40 by combining the output signal of the load 31 and the / EQPR signal. And the fourth and fifth transistors NM4 and NM5 of the level control circuit 40 by combining the inverter INN for inverting the / EPRPR signal and the output signals of the rod 31 and the inverter INV. An output buffer circuit of a semiconductor memory device comprising an AND gate (AND) for controlling. The voltage (Vx, Vy) of a predetermined level when charging and discharging the load 31 can be determined by adjusting the pulse width of the EQPR signal and the magnitude of the precharge voltage (Vpr). An output buffer circuit of a semiconductor memory device, characterized in that.