KR100207449B1 - Power generator for charging bit-line of semiconductor memory - Google Patents

Abstract

A voltage generator is disclosed that charges a bit line electrically connected to a memory sell array to a predetermined precharge level in a short time.

The bit line charging voltage generator according to the present invention includes a voltage generator for generating at least two or more voltages having different levels required for precharging the bit lines; A selector for selecting one of the voltages generated by the voltage generator and providing the bit line to the bit line in response to a control signal applied thereto; And a controller for comparing the voltage of the bit line with a predetermined reference voltage and generating a control signal for controlling the selector according to a comparison result.

The bit line charging voltage generator according to the present invention has an effect of improving the precharge speed by applying a voltage higher than the precharge voltage to the bit line while the potential of the bit line is lower than the precharge voltage.

Description

Voltage Generator for Bit Line Charging in Semiconductor Memory Devices

1 is a circuit diagram showing the configuration of a conventional memory read circuit.

FIG. 2 is a timing diagram showing the operation of the circuit shown in FIG.

3 is a circuit diagram showing the configuration of a conventional voltage generator for charging bit lines.

4 is a circuit diagram showing the configuration of the voltage generator for line charging according to the present invention.

5 is a timing diagram showing an operation when the apparatus shown in FIG. 4 is applied to the circuit shown in FIG.

The present invention relates to a voltage generator for charging a bit line of a semiconductor memory device, and more particularly, to a voltage generator for precharging a bit line electrically connected to a memory sell array to a predetermined level in a short time. .

In a semiconductor memory device, data read from a memory cell appears on a pair of bit lines, which are amplified by a sense amplifier and then output through a data output buffer. At this time, the bit line is preferably precharged to a predetermined level before data transfer.

The reason for this is that when data appears on the bit line, the potential on the bit line suddenly shifts from logic 0 to logic 1 and vice versa, which swings the width of the supply voltage, resulting in peak current. ) Flows.

The conventional bit line charging voltage generator has a problem that its capacity must be very large because all the charges required for precharging must be supplied.

In addition, in view of the instantaneous charge supply capability, there is a problem in that it takes a long time to raise the bit line transitioned to the ground potential back to the precharge level.

It is an object of the present invention to provide an improved voltage generator which has been devised to solve the above problem and which speeds up the precharge of a bit line.

According to an aspect of the present invention, a bit line charging voltage generator includes: a voltage generator configured to generate at least two voltages having different levels required for precharging a bit line; A selector for selecting one of the voltages generated by the voltage generator and providing the bit line to the bit line in response to a control signal applied thereto; And a controller which compares the voltage of the bit line with a predetermined reference voltage and generates a control signal for controlling the selector according to a comparison result. When the voltage of the bit line is less than a predetermined reference voltage, the controller The control unit selects and outputs a voltage having a higher level than the currently applied voltage by controlling the selector, and if it is large, selects and outputs a voltage having a lower level than the currently applied voltage. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a conventional data reading circuit for reading contents written to a memory cell array. The device illustrated in FIG. 1 is configured to measure the voltage level detected by the equalization and precharge unit 12 and the bit lines BL1 and BL2 that equalize and precharge the bit lines BL1 and BL2 connected to the memory cell array 10. And a transfer gate portion 14 and a data output portion 18 for transferring to the sense amplifier 16.

The operation of the apparatus shown in FIG. 1 will be described with reference to the timing diagram shown in FIG. During the active cycle, the contents written to the cell transistors are transmitted to the data output unit 18 through the transfer gate section 14 and the sense amplifier 16, and bit by the operation of the equalization and precharge section 12 during the precharge cycle. Lines BL1 and BL2 are precharged to 1 / 2Vcc level.

When the RASB signal goes low and an active cycle starts, and a predetermined cell transistor is selected by the word line select signal WL and a bit line select signal (not shown), the bit lines BL1 and BL2 are written to the cell transistors. The corresponding voltage is induced.

In this case, when logic 1 is written in the selected cell transistor, since the threshold voltage is negative, when the word line select signal WL applied as the gate bias signal is 0V, the cell transistor is turned on and connected to the bit line ( BL1) falls to ground potential. On the contrary, when logic 0 is written in the selected cell transistor, since the threshold voltage is positive, the cell transistor is in a non-conductive state, and the bit line BL1 connected thereto maintains an initial precharge level of 1 / 2Vcc.

In addition, another bit line BL2 is induced with a voltage having an intermediate level between the cell in which logic 1 is written and the cell in which logic 0 is written by the reference cell.

While the transfer gate control signal ISO remains high, the voltage induced in the bit lines BL1 and BL2 is transferred to the sense amplifier 16.

The sense amplifier 16 is controlled by the sense amplifier control signals LA and LAB to amplify and latch the voltage induced in the bit lines BL1 and BL2. The voltage latched by the sense amplifier 16 is transmitted to the data output unit 18.

When the word line select signal WL and the bit line select signal (not shown) disappear, the selected cell transistor is deactivated.

Next, when the equalization and precharge control signal PIEQ goes low, the precharge cycle starts, and the bit lines BL1 and BL2 are precharged to 1 / 2Vcc by VSBL having the 1 / 2Vcc level. VSBL is produced by a conventional constant voltage generator as shown in FIG.

The device shown in FIG. 3 includes a PMOS transistor 301, an NMOS transistor 302, a PMOS transistor 303, and an NMOS transistor 304 connected in series between a power supply voltage Vcc and a ground voltage Vss. The potential of the first node 1, the second node 2, and the third node 3 is held by a bias circuit composed of The potential of each node 1, 2, 3 is determined according to the size of the Morse transistors 301-304. In addition, the PMOS transistor 301 and the NMOS transistor 304 serve as a resistor, and the resistance value is changed by feedback control to stabilize the output voltage.

In this case, as the potential of the third node 3 is set to 1/2 Vcc, the potential of the first node 1 becomes 1/2 Vcc + Vtn (where Vtn is the threshold voltage of the enMOS transistor 302). The potential of the second node 2 is 1/2 Vcc-Vtp (where Vtp is the threshold voltage of the EnMOS transistor 302). The voltages of the first and second nodes 1 and 2 are applied to the gates of the NMOS transistor 305 and the PMOS transistor 306 which are used for output driving, respectively. Therefore, the output voltage VSBL at the output node 4 is constant at 1 / 2Vcc + Vtn-Vtp (where Vtn is the threshold voltage of the enmos transistor 305 and Vtp is the threshold voltage of the enmos transistor 306). Done.

In the case of the prior art, since the charge required for precharging the bit line must be supplied from the 1 / 2Vcc generator shown in FIG. 3, the capacity of the 1 / 2Vcc generator must be very large.

In terms of instantaneous charge supply capability, there are some limitations, so it takes a lot of time to bring the bit line transitioned to ground potential back to the 1 / 2Vcc level.

In addition, at the start of precharge, the VSBL falls to the potential of the equalized bit line and returns to its original level with the progress of the precharge cycle.

4 is a circuit diagram showing an embodiment of the voltage generator according to the present invention. In FIG. 4, reference numeral 400 denotes a voltage generator, 410 denotes a selector, and 420 denotes a controller.

The voltage generator 400 is similar to that shown in FIG. Vcc applied to the selector 410 in this embodiment is shown separately from the voltage generator 400. However, this does not necessarily mean that the voltage generator 400 must be separate.

In fact, Vcc applied to the selector 410 may be taken at the Vcc terminal of the voltage generator 400 and will be described below as such.

The selector 410 is formed between the PMOS transistor 40 provided between the Vcc output terminal of the voltage generator 400 and the VSBL supply line, and between the 1/2 Vcc output terminal of the voltage generator 400 and the VSBL supply line. The enmos transistor 42 provided is provided. The gates of the PMOS transistor 40 and the NMOS transistor 42 are commonly connected, and the control signal D from the control unit is applied.

The control unit 420 gates the result of the determination of the comparator 50 and the comparator 50 comparing the voltage applied to the VSBL supply line with the reference voltage, and provides the control signal of the selector 410 as the NAND gate 52. ), The NMOS transistor 54 which controls the enable operation period of the comparator 50, the inverter 56 which inputs and inverts the PIVSBL signal and outputs the signal, and the signal provided by the inverter 56 and the RASB signal. And a NOR gate 58 that performs a NOA operation on the gate of the NMOS transistor 54.

Here, 1/2 Vcc output from the voltage generator 400 is applied as the reference voltage of the comparator 50. In the embodiment of FIG. 4, 1/2 Vcc of the voltage generator 400 is applied, but a higher voltage (eg, Vcc) may be used.

The operation of the apparatus shown in FIG. 4 will be described with reference to the timing diagram shown in FIG. The PIVSBL signal is a signal that starts at the time when the PIEQ signal falls to the low level during the active cycle and maintains the high level until the RASB signal returns to the high level as shown in FIG. The controller 420 operates in a section in which the PIVSBL signal is enabled. Specifically, the NOA gate 58 inputs the PIVSBL signal and the RASB signal inverted by the inverter 56 to conduct the NMOS transistor 54 while the PIVSBL is enabled. Accordingly, the comparator 50 operates to output a result of comparing the VSBL applied to the bit line with the reference voltage Vref. The determination result of the comparator 50 is output as the control signal D of the selector 410 through the NAND gate 52. NAND gate 52 is also gated by the PIVSBL signal.

When the PIEQ signal is at a low level, the bit lines BL1 and BL2 start to be equalized and precharged, and then transition to 1 / 2Vcc. At this time, the VSBL becomes less than the original level 1 / 2Vcc under the influence of the bit lines BL1 and BL2, and then gradually recovers to 1 / 2Vcc.

The high level signal is output from the node C of the comparator 50 while the VSBL becomes less than the reference voltage Vref. As a result, the control signal D output from the NAND gate 52 becomes low. Accordingly, the PMOS transistor 40 of the selector 410 is in a conductive state, and the enMOS transistor 42 is in a non-conductive state. Accordingly, Vcc is applied to the bit lines BL1 and BL2. That is, in a section where the bit line level is less than 1/2 Vcc, Vcc is applied instead of 1 / 2Vcc to increase the precharge speed of the bit lines BL1 and BL2.

When the pre-charging of the bit lines BL1 and BL2 proceeds and becomes equal to or greater than the 1/2 Vcc level (under the influence of Vcc), a low level signal is output from the node C of the comparator 50. As a result, the control signal D output from the NAND gate 52 becomes a high level. Therefore, the PMOS transistor 40 of the selector 410 is in a non-conductive state, and the enMOS transistor 42 is in a conductive state. Accordingly, 1/2 Vcc is applied to the bit lines BL1 and BL2. That is, 1 / 2Vcc, which is a normal precharge voltage, is applied in a small section where the level of the bit line is equal to or greater than 1 / 2Vcc.

When the PIVSBL signal is disabled (goes low), the action of the inverter 56 and the NOA gate 58 causes the NMOS transistor 54 to become non-conductive, thereby disabling the comparator 50.

In addition, since the control signal D becomes high by the action of the NAND gate 52, the PMOS transistor 40 of the selector 410 is in a non-conductive state, and the NMOS transistor 42 is in a conductive state. do. As a result, 1 / 2Vcc is continuously output.

Various levels of voltage may be used as the reference potential of the comparator 50. Therefore, various precharge levels can be determined and a constant level can be maintained regardless of the length of the precharge section.

As described above, the bit line charging voltage generator according to the present invention has the effect of improving the precharge rate by applying a voltage higher than the precharge voltage to the bit line while the potential of the bit line is lower than the precharge voltage.

In addition, there is an effect that can achieve a stable memory operation by overcoming the limitation of the instantaneous charge supply capability that can be caused by using a single voltage generator.

Claims (1)

A semiconductor memory device for precharging a bit line connected to a memory cell array to a predetermined level, comprising: a voltage generator configured to generate at least two voltages having different levels required for precharging the bit line; A selector for selecting one of the voltages generated by the voltage generator and providing the bit line to the bit line in response to a control signal applied thereto; And a controller configured to compare the voltage of the bit line with a predetermined reference voltage and generate a control signal for controlling the selector according to a comparison result, wherein the controller is configured such that the voltage of the bit line is a predetermined reference voltage. If the number is smaller, the selector is controlled to select and output a voltage having a higher level than the currently applied voltage. On the contrary, if the larger value, a voltage having a lower level than the currently applied voltage is selected and output. Voltage generator.