KR940005107A

KR940005107A - Video Pattern Generator Using Data

Info

Publication number: KR940005107A
Application number: KR1019920014214A
Authority: KR
Inventors: 오재곤
Original assignee: 강진구; 삼성전자 주식회사
Priority date: 1992-08-07
Filing date: 1992-08-07
Publication date: 1994-03-16
Also published as: KR0140370B1

Abstract

본 발명은 데이타를 이용한 비디오 패턴 제너레이터에 관한 것으로 3.58MHz의 클럭신호를 생성하여 출력하는 클럭발진부와, 상기 클럭 발진회로에서 입력되는 3.58MHz의 클럭을 분주하여 디스플레이장치의 회면에 표시되는 어드레스(Address)를 제어레이터 하는 카운터부와, 상기 카운터의 출력이 1화언일때 상기 카운터의 출력을 조합하여 자동으로 리세트시키는 어드레스 리세트부와, 상기의 카운터에 의해 분주된 어드레스를 주기로하는 8가지 패펀을 저장하였다가 출력하는 8비트의 롬과, 상기 8비트의 롬으로부터 출력되는 8가지의 패턴을 조합하여 비디오 신호로 출력하는 조합증폭부로 구성함으로써 수직동기, 수평동기 및 이퀼라이징 펄스를 혼합한 컴퍼지트 동기신호를 비롯한 8가지의 패턴을 얻을 수 있음은 물론 이들 8가지 패턴을 조합한 데이타들에 의한 비디오 신호를 얻도록 한 것이다.The present invention relates to a video pattern generator using data, comprising: a clock oscillator for generating and outputting a clock signal of 3.58 MHz, and a clock of 3.58 MHz inputted from the clock oscillator circuit to display an address displayed on the surface of a display device. A counter unit for controlling the control unit, an address reset unit for automatically resetting the counter output when the counter output is one language, and eight different punctures each having an address divided by the counter. Composite with vertical sync, horizontal sync, and equalizing pulses, consisting of an 8-bit ROM that stores and outputs a combined amplifier that combines 8 patterns output from the 8-bit ROM and outputs it as a video signal. Eight patterns including synchronization signal can be obtained, as well as data combining these eight patterns To obtain a video signal.

Description

Video Pattern Generator Using Data

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 전체적인 구성을 도시한 블럭도,1 is a block diagram showing the overall configuration of the present invention;

제2도는 수평 펄스신호의 파형도,2 is a waveform diagram of a horizontal pulse signal,

제3도는 수직 펄스신호의 파형도,3 is a waveform diagram of a vertical pulse signal,

제4도는 본 발명의 클럭들의 파형도,4 is a waveform diagram of clocks of the present invention;

제5도는 1화면을 이루는 수직 및 수평동기신호를 나타낸 개략도.5 is a schematic diagram showing vertical and horizontal synchronization signals forming one screen.

Claims

In the video pattern generator, a clock clock signal (AO) through ( A counter 2 for outputting Al4 and an address by a cycle of the clock signals AO to Al4 output from the counter 2 are input, and an address input by a user input to the data terminal is input. ROM 4 for storing eight patterns such as composite synchronous, cross pattern, and mesh pattern according to the user's selection inputted to the data terminal, and clock signals AO to (+) output from the counter unit 2; ROM 4 for storing eight patterns, such as composite synchronization, cross pattern, and mesh pattern, according to a user's selection of input of the earth by the period of Al4), and the counter unit 2 Clock signals (AO) to (Al4) output by 1 The clock signal A2, (A5), (A6), (A7), (A10), (Al2), (Al3), and (Al4) AND gates (Al) to (A7) The address reset unit 3 for resetting the two counters ICI and IC7 of the counter unit 2 by judging by a logical product through the above, and the composite synchronization and switching switch SW stored in the ROM 4. A video pattern generator using data comprising: a combination amplification unit (5) for combining and amplifying seven patterns selected by the < RTI ID = 0.0 >

※ Note: The disclosure is based on the initial application.