KR940004610B1 - Nand type mask rom and fabricating method thereof - Google Patents

Abstract

NAND-type mask ROM constructed in a manner that MOSFETs are connected in series is disclosed, wherein a source and drain of a MOSFET are connected to each other in order to make the MOSFET operate at 0V as depletion-type MOSFET does, the source and drain are connected by a conductive layer which is isolated from a gate electrode and enclosed by a gate electrode, simplifying the manufacturing procedure and maximizing the performance of the depletion-type MOSFET.

Description

NAND-type mask ROM and manufacturing method thereof

1A and 1B show the formation of a NAND type mask ROM according to the first embodiment of the prior art.

2A and 2B show the formation of a NAND type mask ROM according to the second conventional embodiment.

3 is an equivalent circuit diagram of a NAND type mask ROM manufactured by the present invention.

4A to 4G are sectional views showing the manufacturing steps of the NAND mask ROM according to the present invention.

5 is a cross-sectional view of a NAND type mask ROM according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1: P-type substrate 2: Gate oxide film

3: polygate 4: insulation layer

5: N + Diffusion Area 5A: N-Diffusion Area

6: insulation spacer 7: conductive layer

8: photoresist pattern 9: insulating layer

10 depletion transistor 20 increase transistor

30: mask

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND mask ROM of a highly integrated semiconductor device and a method of manufacturing the same, and more particularly, to a NAND mask ROM in which a source and a drain of a transistor to be used as a depletion transistor are interconnected with a conductive layer.

Mask ROM, unlike EPROM and EEPROM, does not allow the user to write data arbitrarily, and the code that the user wants to use is fixed by process technology during ROM production. It only has a read function for.

Mask ROM is classified into a NOR or NAND type according to a cell array method, and the most recently used mask type is a NAND type. Since the NAND type combines transistors in series connection state, logical "0" and "1" according to the code generally consist of a depletion transistor and an enhancement transistor.

Therefore, since the NAND type mask ROM is to input the code by a combination of the depletion type and the incremental type transistors, a method for manufacturing the NAND mask ROM in a short time is required to meet the user's requirements.

In the first embodiment of the prior art, as shown in FIGS. 1A and 1B, a recess is formed in a portion of the polygate 3 with a code mask formed according to a user's request in the portion where the depletion transistor 10 is to be formed. By forming the N + diffusion region (4) formed by the ion implantation process of the post-process by forming the interconnection under the polygate (3) to realize the ON state. An increase transistor 20 is formed on the side of the depletion transistor 10. However, the first embodiment is difficult to apply due to the possibility that the polygate is completely disconnected in the micro pattern technology currently used, and since the polygate is formed with a code according to the user's request from the polygate manufacturing process, the device is manufactured in a short time. It is difficult to do.

2A and 2B show a state in which the depletion transistor 10 and the increment transistor 20 are formed according to the second embodiment of the prior art, in order to form the NAND cell entirely in the N-channel. A low concentration N-type impurity is ion-implanted in the upper portion of the P-type substrate 1 to form polygates 3, respectively, and then a high concentration N-type impurity is injected into the P-type substrate 1 to form the N + diffusion region 5. The photoresist pattern 8, which is a mask 30, is selectively opened only at the portion where the depletion transistor 10 is to be formed, and the P-type impurity is deposited on the exposed P-type substrate 1. It is a method of converting the depletion transistor 20 into the incremental transistor 10 by ion implantation with energy.

However, in the second embodiment, the depletion transistors are formed in all regions, and then an increase transistor is selectively formed by using a mask as a post-process, but the manufacturing process is fast, but the characteristics of the depletion transistor and the increase transistor (compensated transistor) Are so closely related that it is very difficult to control them properly. Because depletion transistors have a higher concentration and depth of N-, the current increases, but it becomes very difficult when excessive concentrations and depths are used again to increase transistors.

Accordingly, an object of the present invention is to solve the problems of the prior art and to provide a manufacturing method and a NAND mask ROM for manufacturing a NAND mask ROM simply and quickly according to a user's request.

According to the present invention, in order to connect a source and a drain of a predetermined MOSFET to a conductive layer, sequentially forming a gate oxide film, a polysilicon for a gate electrode, and an insulating layer on a P-type substrate, and forming the insulating layer by a gate electrode pattern process. Forming a polygate by removing a predetermined portion of the gate silicon polysilicon; implanting N-type low concentration impurities into the substrate to form an N-diffusion region; and forming an insulating spacer on the sidewall of the polygate. Next, forming an N + diffusion region by ion implanting an N-type high concentration impurity into the substrate, removing a gate oxide layer on the N + diffusion region, and then forming a conductive layer on the entire structure, Form a predetermined photoresist pattern to leave the conductive layer connected to the drain and remove the exposed conductive layer. Is characterized in that it comprises a step, forming an insulating layer on the entire structure.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 3 is an equivalent circuit showing the NAND type mask ROM according to the present invention, and shows the transistor source and drain of the portion to be the depletion transistor 10 interconnected.

4A to 4G are cross-sectional views showing steps of manufacturing a NAND type mask ROM according to the present invention.

FIG. 4B shows a pattern of the polygate 3 by removing the insulating layer 4 and the polysilicon layer 3A for the gate electrode of the predetermined portion by the gate electrode pattern process, and then forming an N-type low concentration impurity. It is sectional drawing of the state which ion-implanted in the board | substrate 1 and formed the N-diffusion area | region 5A.

4C shows an insulating spacer 6 formed on the sidewalls of the polygate 3 and the insulating layer 4, and the N + diffusion region 5 is formed by injecting N-type highly concentrated impurities into the P-type substrate 1. It is a cross section.

4D is a cross-sectional view of a state where the gate oxide film 2 above the N + diffusion region 5 is removed.

4E is a cross-sectional view of the conductive layer 7, for example, a doped polysilicon layer formed on the entire structure.

FIG. 4f shows the photoresist pattern 8 is formed to take advantage of the operation of the depletion transistor turned on at zero volts according to user requirements, and then the exposed conductive layer 7 is removed to form a conductive layer ( 7) is a cross-sectional view of the state in which the conductive layer 7 is interconnected with the source and drain of the intended transistor.

4G is a cross-sectional view of a state in which the insulating layer 9 is formed on the entire structure, and the subsequent steps are the same as those of forming a general NAND type mask ROM.

5 is a cross-sectional view showing the formation of the N + diffusion region 5 according to another embodiment of the manufacturing method of the present invention, and instead of forming the N + diffusion region 5 as shown in FIGS. 4C and 4E. After removing the gate oxide film 3 on the upper portion of the N-diffusion region 5A, the conductive layer 7 is formed on the entire structure, and the high concentration impurity of the conductive layer 7 is transferred to the N-diffusion region 5A by a heat treatment process. In this method, the N + diffusion region 5 is formed by diffusion.

As described above, the present invention is simple to manufacture by forming all the transistors and then forming codes according to user requirements, and maximizes the efficacy of the depletion transistor by connecting the source and drain to the conductive layer, and the cumbersome process as in the prior art. By not applying the method and device technology, the margin of the process method and device is improved.

Claims (3)

In a NAND type mask ROM composed of MOSFETs connected in series, the source and drain of the predetermined MOSFETs are interconnected to be turned on at 0V like a depletion transistor for each predetermined MOSFET, but the gates are insulated from the gate electrodes. A NAND type mask ROM characterized in that the electrode is connected to a source and a drain at the lower side by a conductive layer surrounded by an electrode. In the method of manufacturing a NAND mask ROM in which MOSFETs are connected in series, a gate oxide film, a polysilicon for a gate electrode, and an insulating layer are sequentially formed on a P-type substrate in order to connect a source and a drain of a predetermined MOSFET to a conductive layer. Forming a poly gate by removing a predetermined portion of the insulating layer and the polysilicon for the gate electrode through a gate electrode pattern process, and forming an N-diffusion region by ion implanting N-type low concentration impurities into a substrate And forming an insulating spacer on the sidewalls of the polygate, and implanting N-type highly doped impurities into the substrate to form an N + diffusion region, removing a gate oxide layer on the N + diffusion region, and then conducting an upper portion of the entire structure. Forming a layer and forming a layer to leave a conductive layer connecting the source and drain of the predetermined transistor. Removing the exposed electrically conductive layer to form a resist pattern and, NAND-type mask ROM manufacturing method characterized by comprising the steps of: forming an insulating layer on the upper structure. The substrate of claim 2, wherein the N + diffusion region is formed by depositing a conductive layer in a post-process, instead of ion implanting an N-type high concentration impurity, followed by a heat treatment process. NAND type mask ROM manufacturing method comprising the step of diffusing to form an N + diffusion region.