KR940004591U - 수평동기신호 안정화 회로 - Google Patents

수평동기신호 안정화 회로

Info

Publication number
KR940004591U
KR940004591U KR2019920013470U KR920013470U KR940004591U KR 940004591 U KR940004591 U KR 940004591U KR 2019920013470 U KR2019920013470 U KR 2019920013470U KR 920013470 U KR920013470 U KR 920013470U KR 940004591 U KR940004591 U KR 940004591U
Authority
KR
South Korea
Prior art keywords
sync signal
horizontal sync
stabilization circuit
signal stabilization
circuit
Prior art date
Application number
KR2019920013470U
Other languages
English (en)
Other versions
KR950007876Y1 (ko
Inventor
최창원
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR92013470U priority Critical patent/KR950007876Y1/ko
Publication of KR940004591U publication Critical patent/KR940004591U/ko
Application granted granted Critical
Publication of KR950007876Y1 publication Critical patent/KR950007876Y1/ko

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Synchronizing For Television (AREA)
KR92013470U 1992-07-21 1992-07-21 수평동기신호 안정화 회로 KR950007876Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92013470U KR950007876Y1 (ko) 1992-07-21 1992-07-21 수평동기신호 안정화 회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92013470U KR950007876Y1 (ko) 1992-07-21 1992-07-21 수평동기신호 안정화 회로

Publications (2)

Publication Number Publication Date
KR940004591U true KR940004591U (ko) 1994-02-24
KR950007876Y1 KR950007876Y1 (ko) 1995-09-22

Family

ID=19337089

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92013470U KR950007876Y1 (ko) 1992-07-21 1992-07-21 수평동기신호 안정화 회로

Country Status (1)

Country Link
KR (1) KR950007876Y1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100707258B1 (ko) * 2004-09-01 2007-04-13 삼성전자주식회사 디스플레이장치

Also Published As

Publication number Publication date
KR950007876Y1 (ko) 1995-09-22

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