KR940004265Y1 - Control circuit for video memory writing - Google Patents

Abstract

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Description

Write Mode Control Circuit of Video Memory

1 is a schematic diagram of a write mode control of a conventional video memory.

2 is a data bit truth table of a rotation / function selection register.

3A is a screen selectivity by data of the central processing unit, and b is a screen selectivity by latch data.

4A to 4D show screen configurations by a logical combination of a central processing unit and latch unit data.

5 is a write mode control circuit diagram of a video memory of the present invention.

6a to d is a screen configuration diagram according to the present invention.

* Explanation of symbols for main parts of the drawings

10: control signal generator 20: data operation unit

30: function selector 40: multiplexer

AD1-AD9: AND gate OR1: OA gate

XOR1: Exclusive Oagate NOR1: Noagate

I1-I3: Inverter

The present invention relates to the control of the write mode of the video memory, and in particular, it adds the NOT operation function to the functions provided by the write mode signal, and the OR, OR, Exclusive OR, and replace functions to use various screens. The present invention relates to a write mode control circuit of a video memory, which is suitable for the purpose.

FIG. 1 is a schematic diagram of a write mode control of a conventional video memory. As shown therein, a latch unit 1 for temporarily storing data of a memory plan 2, a rotation order of data, and a replace ( Replace, End, Ora, and Exclusive Ora Data rotation / function selection registers 3 and bit mask registers 5 to select the functions of the conventional circuits configured as shown in FIGS. If described with reference to:

When data of the central processing unit (CPU) is input to the register 4, first, the CPU data is rotated by the value stored in the data bits D0-D2 of the data rotation / function selection register 3, and then the register ( In accordance with the value of the data bits D3 and D4 of 3), an AND, OR, or exclusive function with the data value output to the latch unit 1 is performed or the data of the latch unit 1 is ignored and the CPU Performs a replace function that outputs only the data of the.

At this time, the function performed by the value of the data bits (D3, D4) of the data rotation / function selection register 3 is shown in Figure 2, the final result value after performing such an operation function is again stored in memory Written in plan 2, the value of bit mask register 5 must be referenced prior to performing the write operation.

That is, the final result value of the operation is written to the position of the bit having the value "1" among the values of the register 5, and stored in the latch unit 1 at the position of the bit having the value "0". The original data is supplied and the value is written.

For example, when the data of the CPU and the data of the latch unit 1 are equal to the hatched portions of FIGS. 3a and b, respectively, the 3, 4 bits (D3) and (D4) of the data rotation / function selection register 3 are used. If the value is the same as in the table of FIG. 2, the screen is configured as shown in FIG. 4A in replace mode, FIG. 4B in AND mode, FIG. 4C in OR mode, and FIG. 4D in EXCLUSIVE OR mode.

However, in such a conventional circuit, the write mode logic value "0" applied to a predetermined bit of the data rotation / function selection register is limited to four functions so that a sufficient service cannot be provided to the user. There was this.

The present invention is designed to double the existing writing mode selection function without causing a separate cost increase in order to solve such a conventional defect will be described in detail with reference to the accompanying drawings.

5 is a block diagram of the write mode control circuit of the video memory of the present invention, as shown therein, consisting of the AND gates AD1-AD4 and the inverters I1, I2, and the data bits of the data rotation / function selection register. A selection control signal generator 10 for outputting control signals of replace, OR, AND, and exclusive OR by logically combining the values of (D3) and (D4), and the exclusive wargate (XOR1) and the oragate. (OR1) and AND gates (AD5), and the data operation unit 20 for performing replacement, OR, AND, and exclusive OR of the O-bit latch data (LO) and CPU data (CO), and the AND gate ( AD6-AD7), the NOA gate (NOR1), and the inverter (I3), and according to the output control signal of the control signal generator 10, replace, or ,, and, or exclusive of the data operation unit 30. A function selection unit 30 for selectively outputting one of the outputs, and data According to the present invention configured as a multiplex 40 for outputting the output data of the function selection unit 30 as it is or inverting the output data according to the data value input from the predetermined bit D5 of the all / function selection register. The action and effect will be described in detail with reference to FIGS. 2 and 3, 4 and 6 as follows.

For example, when the 3, 4-bit data D3 and D4 of the rotation / function selection register are 0 and 0, respectively, the AND gate AD1 of the AND gates AD1 to AD4 of the control signal generator 10 is set to 0 and 0, respectively. ) 1 (high potential logic value) is outputted only, and 0 (low potential logic value) is outputted to all the remaining AND gates AD2-AD4, so that the AND gates AD5 and OA gate OR1 of the data operation unit 20 are output. ), While the output value of the exclusive oragate XOR1 is invalid, only the 0-bit data CO of the CPU supplied to the AND gate AD6 becomes valid, and the output of the selected AND gate AD6 is thus valid. The NOR gate NOR1, the inverter I3, and the multiplexer 40 output the value of the final result data written to the memory plan.

Second, when the 3, 4 bit data D3 and D4 of the rotation / function selection register are 0 and 1, respectively, the AND gates AD1 and AD2 excluding the AND gate AD3 of the control signal generator 10. And 0 are all output to AD4, so only the output of the OR gate OR1 of the data operation unit 20 becomes valid, so the 0-bit latch data LO and the CPU data CO input to the OR gate OR1 are valid. ) Is generated by the oring operation.

Third, when the 3, 4 bit data D3 and D4 of the rotation / function selection register are 1 and 0, respectively, the AND gates AD1 and AD3 except for the AND gate AD2 of the control signal generator 10 are set. And 0 are all output to AD4, so only the output of the AND gate AD5 of the data operation unit 20 is valid, and thus the 0-bit latch data LO and the CPU data CO input to the AND gate AD5. ) Is ANDed and output.

Fourth, when the 3, 4-bit data D3 and D4 of the rotation / function selection register are 1 and 1, respectively, the AND gates AD1 and AD2 except for the AND gate AD4 of the control signal generator 10, respectively. 0 is output to all of AD3), so that only the output of the exclusive OR gate XOR1 of the data operation unit 20 becomes valid. Therefore, the 0 bit latch data LO input to the exclusive OR gate XOR1 is valid. ) And CPU data (CO) are computed and output as an exclusive ora.

As a result, the zero-bit latch data (LO) and the CPU data (CO) are replaced, ora, and / or included according to the 3 and 4 bit data (D3) and (D4) values of the rotation / function selection register as described above. 5 of the data rotation / function selection registers which are operated by sheave or operation, and the data of the CPU and the latch portion are the same as the hatched portions of FIGS. If the third and fourth bit values of the rotation / function selection register are the same as in the table of FIG. 2 with the first bit (D5) equal to 0, FIG. 4C in the replace mode, and FIG. 4D when in the exclusive or mode. The screen is configured as shown.

However, when the fifth bit (D5) value of the data rotation / function selection register supplied as the selection control signal of the multiplexer 40 is supplied as 1, the multiplexer 40 outputs the data to the function selection unit 30. Since the value is inverted and outputted, the screen as shown in FIG. 4 can be inverted to the screen as shown in FIG.

As described in detail above, the present invention has an advantage of providing a display mode twice as large as that by using the data bits of the multiplexer and the data rotation / function selection register without additional hardware.

Claims (1)

A selection control signal generator 10 for outputting control signals of replace, OR, AND, and exclusive OR by logically combining data bit (D3) and (D4) values of the data rotation / function selection register and 0 bits The data operation unit 20 performs a replace, or, end, or exclusive OR operation on the latch data LO and the CPU data CO, and the data operation unit according to an output control signal of the control signal generator 10. A function selector 30 for selectively outputting one of the replace, oar, end, and exclusive oar outputs of < RTI ID = 0.0 > 30) < / RTI > and a data value input from a predetermined bit D5 of the data rotation / function select register. And a multiplexer (40) outputting the output data of the function selection unit (30) as it is or inverting the output data.