KR940004251B1 - Manufacturing method of finishing of semiconductor device - Google Patents

Abstract

depositing a first passivation layer on a semiconductor wafer on which a conductive pattern is formed; depositing a second passivation layer on the first passivation layer; selectively removing the first and second passivation layers to open pad portion and repair fuze portion for pre-laser and assembly process; and polishing the back of the semiconductor wafer, thereby enhancing the probing characteristic.

Description

Manufacturing method of finish of semiconductor device

1 is a flow chart of a conventional EDS inspection process.

2 is a flow chart of the EDS inspection process of the present invention.

3 is a profile of a conventional manufacturing process for each EDS inspection process.

4 is a profile of the final manufacturing process for each EDS inspection process of the present invention.

5a and b are plan and cross-sectional views of a conventional pad portion.

6A and 6B are a plan view and a sectional view of the pad portion of the present invention.

7 is a cross-sectional view of a conventional redundancy fuse.

8 is a cross-sectional view of the redundant fuse portion of the present invention.

Figure 9a is a diagram of a conventional pre-laser test result mapped to a wafer.

FIG. 9B is a diagram in which the pre-laser inspection result data of FIG. 9A is extracted and mapped only to BIN 2 by a binary telephone program according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a wafer inspection process for improving productivity by simplifying the quality and defect inspection and repair processes of a memory device such as a DRAM or an SRAM with a redundancy circuit. It is about.

Recent advances in the design of semiconductor memory devices and the development of microfabrication technologies have enabled higher integration and multi-functionality of mega units. However, as the distance between the line widths is shortened due to the high integration of semiconductor memory devices, the possibility of process defects is increasing throughout the manufacturing process, resulting in a further decrease in yield. In particular, in the semiconductor memory device using a process having a line width of 1 μm or less, the above-described process defect problem is further exacerbated. Therefore, semiconductor manufacturers inspect each chip in the wafer state to improve yield by suppressing yield decrease due to process defects, and to reserve and repair the repairable chips caused by small process defects. Redundancy technology is used to embed a block and replace it with a spare circuit when a small defect is included due to a minor process defect in a regular circuit.

For example, in a semiconductor memory circuit, spare blocks of spare rows and spare columns are integrated on a chip, and a row / column block including defective bits of a rectified cell array is replaced with a spare row / column block. Such a redundancy technique is very effective in DRAM or SRAM in which many cells of the same function are arranged. In order to replace a bad row / column with a bad bit of a memory device with a normal spare row / column, a program element and a program method for deactivating the defective row / column and activating the spare row / column are required. Typical well-known redundancy program elements and programming methods include a fuse composed of polysilicon resistors, a residual method of electrically melting the fuse, and a link composed of polysilicon or polysides and a laser beam. There is a laser beam method that directly irradiates with a melt.

The current fuse method requires a large current driving transistor for a fuse blown, a control circuit, a special pad for supplying current, and so on, the chip takes up a large area on the chip, and the program access time is delayed. The maintenance equipment is inexpensive and the fuse part is covered with a protective film, so the reliability is maintained.

The laser method has a problem that the initial cost is high because the inspection and repair equipment is very expensive, and a high total process completion time is required for the stability and accurate positioning of the laser beam. Since it can be installed in a small area, the redundancy circuit can be easily designed and the chip area can be used economically. Therefore, in recent years, the use of the laser beam method is increasing in accordance with the trend of ultra miniaturization and high integration of semiconductor memories.

A flowchart of a conventional EDS (Electric Digital System) inspection method for a semiconductor memory device using the laser beam redundancy method, that is, a inspection method for discriminating good or bad goods in a wafer state is shown for each block in FIG.

Referring to FIG. 1, the EDS test distinguishes a prime die from a completely non-repairable chip with a repairable die and pre-lasers to find defective address information on the repairable chip. laser process (103) for replacing defective address with redundancy with repair information found in the pre-laser process, and prime good and repair It consists of a Final Wafer Sorting Test (105) in the final wafer which distinguishes the finished good die and inking the bad die.

In the conventional EDS inspection method, the laser repair is performed before and after, and the pre-laser inspection and the inspection of the good and bad products in the final wafer are performed twice, and all the chips in the wafer are inspected.

FIG. 3 is a process cross-sectional view of each block of the EDS test method of the probing pad and the repair fuse for the conventional electrical property test.

Referring to FIG. 3, after the element forming process is completed on the silicon wafer, a normal metal process is performed on the wafer on which the oxide film is formed on the entire surface. Subsequently, a PSG protective film is deposited on the wafer on which the metal pattern layer is formed (step 301), and the PSG protective film is selectively etched by the first photolithography process to turn off the fabrication site and the laser repair fuse area (step 302). However, even if the PSG protective layer on the pad portion is etched by 30%, the oxide layer under the PSG protective layer is not completely removed. The remaining oxide film is melted and broken together with a conductive film (eg, a high melting point metal such as polysilicon or silicide) by a laser beam during laser repair. Next, the wafer is loaded on the probe device, the probe is contacted on the opened pad, and the pre-laser inspection process is performed through the tester device (step 303). Subsequently, a wafer map is made according to the result of the pre-laser inspection shown in FIG. 9 indicating whether chips on the wafer are good or bad. After the pre-laser inspection process is completed, the wafer is loaded into the laser equipment for laser repair, and the laser equipment finds the repairable chips (indicated by R of FIG. 9) according to the transmitted pre-laser inspection results, and selects a predetermined link. It irradiates with a laser beam and melts, deactivating a bad row / column, and activating a normal preliminary row / column to produce a good product. In this way, the laser repaired wafer is loaded on the deposition equipment again and the nitride protective film is deposited on the entire surface (step 304). This nitride protective film is intended to protect the melted link portion from physical impacts from outside, humidity, temperature or other contamination in the process.

Subsequently, the nitride protective film on the pad portion is removed by a second photolithography process, and the pad is opened to provide a portion to which the metal wire is connected during assembly (step 305). At this time, in order to reliably remove the nitride protective film on the pad portion, the etching is performed by about 30%. Since the laser repair fuse portion is closed during the second photolithography process, the nitride protective layer remains thereon. Next, a good and bad inspection process in the final wafer, which is an electrical property test, is performed through a back-lap process of physically polishing the back surface of the wafer (step 306). In the final good and bad inspection process, only dies on the wafer are sorted out and all dies on the wafer are scanned automatically to package only the dies, and each die is automatically tested. Inking dots about 2 mil in diameter are marked as defective. Thereafter, the semiconductor memory device is completed through a normal baking process and an assembly process.

The conventional wafer inspection process described above has a two-step process of inspection-processing-processing-inspection, which is very likely to be contaminated from dust and the like, and has a problem in that the quality and reliability of the product are deteriorated if the clean room state is not maintained well. . In addition, since the two-step process of the process-inspection cannot be shortened through time. In addition, after pre-repair sample test is performed with only pre-laser inspection results, skipping if the product is more than 95% and inking to the bad die with wafer map of the pre-laser result without inspecting whether the repaired dies are properly repaired. As a result, a decrease in yield occurs when inspecting a package by the number of unrepaired dies, and a reduction in package yield due to defects in the redundancy circuit itself or cutting miss during laser repair cannot be coped with.

Therefore, a method for omitting the final yield / bad classification step while improving the package yield in the wafer inspection process of the redundant memory products has emerged as an essential problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a wafer inspection process of a semiconductor device which can omit the step of classifying defective or defective products in the final wafer in order to solve the problems of the above-described techniques.

In order to achieve the above object, the present invention comprises the steps of electrically pre-laser inspection on all the chips on the wafer is completed memory manufacturing process; Repairing the defective die using a laser beam; And after the laser repair, if the good quality of the product is less than 95% after performing the BIN2 inspection and offline inking process if the good quality is more than 95% in the sample inspection, the offline inking process immediately without going through the BIN2 inspection process It provides a method for inspecting a wafer of a semiconductor device, characterized in that it comprises the step of selecting the defective die.

Therefore, the present invention can improve productivity by simplifying the process by performing the wafer processing and the wafer inspection process only once.

Among the preconditions to be solved in order to achieve the above object,

First, mask alignment should be possible with respect to the wafer alignment target in the presence of the second nitride protective film on the PSG (Phospo-Silicate Glass) film.

Second, the cutting conditions of the redundancy connection fuses with the secondary protective film formed after the back-lap should be set.

Third, simultaneous etching conditions of the PSG film and the nitride protective film should be set.

Fourth, there should be no reliability problem that can be caused during the fuse connection between the pad and the repair die while the first and second protective films are open.

Fifth, a BIN2 test program for accessing and inspecting only a repairable die among prelaser test results should be developed.

Sixth, pre-laser optimization conditions for improving package yield should be set.

In addition, in order to shorten the inspection time without the cumulative yield reduction and quality deterioration compared to the conventional process with the above-described conditions, the following problems must be solved.

First, passivation and backside polishing should be carried out in the wafer fabrication process before repairing, and then laser repairing should be possible without quality deterioration problem.

Second, Danish, which inspects all chips in the inspection of defective and defective products in the wafer, BIN2 inspection program that can access and inspect only BIN2 with pre-laser inspection results, and remote inking with prelaser inspection results. Need to develop off-line inking program.

Third, there should be no reduction in package cumulative yield than the conventional two inspections with only one pre-laser inspection.

A simplified flowchart of the EDS inspection process according to the present invention, which improves the above-described problems and conditions, is shown block by block as shown in FIG.

Referring to FIG. 2, in the wafer inspection process, the two inspection processes of the conventional pre-laser inspection and the final in-wafer good / bad product screening inspection are also made possible by one pre-laser inspection process 202. As a result, the through-put time of the process is greatly shortened, and the productivity of wafer inspection is improved by 50% or more. In addition, by optimizing the pre-laser inspection (202) conditions, it is possible to improve the package cumulative yield with only one inspection.

Figure 4 is a process cross-sectional view of each block of the EDS inspection method of the probing pad and the repair fuse according to the present invention as shown in FIG.

Referring to Figure 4, the flow of the wafer inspection process according to the present invention includes the steps of opening the PSG protective film on the pad and boss fuse area (401), pre-laser inspection step (402), laser repair step (403), and A good and bad screening test step 404 is performed in the final wafer. Comparing this with the conventional process shown in FIG. 3, it can be seen that the first photolithography process 302 and the intermediate electrical property inspection process 303 are omitted. That is, all inspections are possible with only one pre-laser inspection process 404 under optimized inspection conditions. In other words, the pre-laser inspection process 404 of the present invention includes both the electrical property inspection process 303 and the good and bad screening inspection process 306 in the final wafer.

5A-B and 6A-B are a plan view and a cross-sectional view of a pad portion according to the conventional method and the present invention, respectively, and FIGS. 7 and 8 are cross-sectional views of the redundant fuse portion according to the conventional method and the present invention, respectively. .

Referring to the conventional methods shown in FIGS. 5A-B and 7, a link formed of a polysilicon 74 and a high melting point metal 73 is formed on a silicon wafer 77 via an insulating film 76. Next, an interlayer insulating film 75 is formed on the links 73 and 74, and a pad 70 made of a metal material such as aluminum is formed on the interlayer insulating film 75. Then, a PSG passivation layer 78 having a thickness of about 6,000 Å was deposited on the pad 70, and the PSG passivation layer 78 was selectively removed by a first photolithography process. The pads 70 and the links 73 and 74 were then removed. Open). Next, after performing a pre-laser inspection process, a nitride protective film 71 having a thickness of about 6,000 Å is deposited on the entire surface of the wafer, and the nitride protective film 71 is selectively etched by a second photolithography process to thereby pad the pad 70. Open Subsequently, a process of screening for good and bad products in the final wafer is performed (not shown in FIG. 7 denotes an interlayer insulating film).

In contrast, referring to the present invention shown in FIGS. 6A-B and 8, a link made of polysilicon 84 and a high melting point metal 83 is formed on the silicon wafer 87 via an insulating film 86. Next, an interlayer insulating layer 85 is formed on the links 83 and 84, and a pad 60 made of a metal material such as aluminum is formed on the interlayer insulating layer 85. Subsequently, the PSG passivation layer 62 and the nitride passivation layer 61 are sequentially deposited on the pad 60, and the nitride passivation layer 61 and the PSG passivation layer 62 are selectively removed by a photolithography process. Open At this time, in order to make the thickness of the oxide film on the links 83 and 84 less than 8,000 kPa necessary for the laser repair, the upper portions of the interlayer insulating film 85 remain in place. The thickness of the oxide film is less than about 5,000 kPa. Thus, by making the portions on the links 83 and 84 thin through over etching, the cutting miss rate is reduced.

As described above, in the present invention, the PSG protective film and the nitride protective film are simultaneously etched to shorten the conventional two processing steps to one processing step, thereby greatly reducing the processing time. In addition, the PSG protective film and the nitride protective film are present on the alignment mark at the time of repair of the subsequent laser, so it is difficult to accurately identify the alignment mark due to the identification of the alignment mark, but it is expected that the alignment mark is changed by changing the reticle. Opening at the same time improves product quality.

As described above, in the present invention, the following various effects can be obtained by simplifying and optimizing the wafer inspection process as compared with the conventional method.

1. As shown in the following [Table 1], the manufacturing process and wafer inspection process time can be shortened by more than 17 hours per lot compared to the conventional method by manufacturing a process simplification reticle from the device development stage In the case of mass production, the productivity of inspection process can be improved by more than 50%.

TABLE 1

Application of the process reticle of the present invention when using two conventional photo-etching reticles and the process simplification reticle

2. The passivation layer disappeared after laser repair of the connection fuse, which was a concern for reliability problems that may occur due to high temperature, high humidity, or thermal shock, but compared to the conventional wafer inspection process, PRT (Production Reliability Test) and PCT (Pressure Cooker Test) In the reliability test, more improved results were obtained.

3. In the BIN2 inspection program of the present invention, if the yield is less than 95% after performing the laser inspection with the pre-laser inspection result, the pre-laser inspection result (see FIG. 9A). Inking to the bad die using the data shown in Fig. 1 causes a decrease in yield during package inspection as much as an unrepaired die. Therefore, inspection of the BIN2 die is necessary when the thickness of the PSG protective film is more than 8,000 [mu] s or when the redundancy itself is defective or repaired, or to eliminate the failure mode on the laser. However, it takes too much time to inspect the die in the wafer, so selecting only the repairable die, BIN2 die, can reduce the wafer inspection time by 70% or more. Until now, it was impossible to perform the inspection by searching only the selected X and Y coordinates of the BIN2 die, but in the present invention, the wafer is extracted by extracting only the BIN2 die using a conversion program from the data obtained by the conventional pre-laser inspection results. We have developed a Binary Conversion Program that can be mapped to phases (see also Figure 9b). In addition, the converted mapping data (Fig. 9b) was downloaded to the register again, and only the BIN2 die was inspected while communicating with the tester using only the X and Y coordinates of the BIN2.

4. The off-line inking program of the present invention, unlike the conventional on-line inking program that inks while performing the inspection in real time, performs only the inspection first and then the X, Y coordinate and Only the bad die is inked using the computer with the data storage result. The off-line inking program is faster and easier to control than the on-line inking because the dot size is uniform, productivity is greatly improved due to the reduction of gas time due to Inker problems, and automation. Is an effective way. Table 2 below shows the advantages and disadvantages of the off-line inking of the present invention compared to the conventional on-line inking.

TABLE 2

Advantages and disadvantages of off-line inking of the present invention compared to conventional on-line inking

5. As a method to set the optimization condition of the pre-laser inspection that can improve the cumulative yield with only one laser inspection, firstly, it is necessary to find the die as a condition that will not be recognized as defective considering the influence of noise in the wafer state. Second, find the temperature point deteriorated for each variable according to the temperature of the device and determine the one-time temperature condition. Third, apply the most vulnerable inspection fragrance with a lot of bad factors in the package inspection to the maintenance inspection. Redundancy can be replaced by conservative chips to improve not only the package yield but also the cumulative yield itself.

The main causes of defects in package inspection include pattern sensitivity, cell disturb, refresh sensitivity, dimming of the sense amplifier, access time, open / short circuit, and input / output leakage current. According to the present invention, when the optimization conditions for improving the cumulative number are selected while blocking the above causes of defects in the package inspection as well as the one-time inspection in the package inspection as well as applying the process simplification, the result of applying the conditions of the following [Table 4] As shown in [Table 3], the test cumulative yield was improved by 4.6% compared to the conventional condition.

TABLE 3

Conventional Conditions VS Yield Status by Steps Applied to the Process Simplification Optimization

* P / L: Pre-Laser Test, P / B: Pre-Burn Test, H / S: Hot Sort Test, Cun Yield: Cumulative Yield, PRT: Preduction Reliability Test.

TABLE 4

Conventional Process VS Process Simplification Optimization Condition Comparison Table of the Present Invention

5. One test step can improve pad probing quality and zero probe particle and wafer particle.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

As described above, according to the present invention, in the wafer inspection method of the semiconductor memory device using the laser fuse redundancy method, the conventional pre-laser inspection and the two inspections of the screening of defective or defective products in the final wafer can be performed in one inspection. . As a result, the inspection process processing time was significantly shortened and the productivity of wafer inspection was improved.

In addition, by optimizing the pre-laser inspection conditions, the package cumulative yield could be improved by only one inspection.

In addition, it is possible to repair defective dies that may occur in the nitride protective film process, thereby improving yields, and laser and pre-laser fabrication by remote inspection and inking.

In addition, inking defects due to inker defects generated during on-line inking are reduced, and the quality is improved by omitting the inking.

In addition, since the pad damage and the oxide film exposure caused by the two probing during the two inspections are prevented, it is possible to improve the characteristics of the probing.

When the present invention is applied to a wafer inspection process of a nonvolatile memory device and a semiconductor memory device having no redundancy, it is apparent that a person skilled in the art can easily implement the present invention.

Claims (6)

Depositing a first passivation layer on the semiconductor wafer on which the conductive layer pattern is formed; Depositing a second passivation layer on the first passivation layer; Selectively removing the first and second passivation layers by a photolithography process to open the pad portion and the repair fuse portion for pre-laser inspection and assembly processes; And back polishing the semiconductor wafer. The method of claim 1, wherein a pad portion capable of simultaneously etching two passivation layers is formed on the reticle mask to selectively remove the first and second passivation layers. 2 A method for manufacturing a finish of a semiconductor device, characterized in that the protective film is removed in the same way. The method of claim 2, wherein the second and first passivation layers are sequentially etched. The method of claim 1, wherein the pad portion and the repair fuse portion are simultaneously opened. The method of claim 1, wherein the film thickness of the repair fuse portion is excessively etched the second and the first protective film in order to reduce the disconnection defect rate during redundancy repair, to form a film thickness on the repair fuse portion to 8,000 kPa or less A method of manufacturing a finish of a semiconductor device. The semiconductor device of claim 1, wherein the first and second passivation layers existing on the alignment target of the wafer are selectively removed by a photolithography process using another reticle to open the alignment target. Finish manufacturing method.