JP2000174082A - Semiconductor wafer and method for inspecting its defect - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor wafer where a light level can be set accurately and a defect can be inspected efficiently in the inspection process of the semiconductor wafer. SOLUTION: A plurality of pattern areas 20a-20e that are regions of different reflection factors are formed at a specific region, such as the region of a scribe line 24 of a semiconductor wafer for every chip 22 to be inspected. One of pattern areas 20a-20e is read, and a light level is set and then an inspection region on the chip 22 is scanned. The scanned image is converted to a 256-gradation gray level, and the data is plotted for each pixel to create an image. The created images are overlapped each other, and the difference of the images is obtained, thus the presence or absence of a defect is judged, and hence accurately setting a light level and objectively making comparison with other inspection regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer and a semiconductor wafer defect inspection method for determining the presence or absence of a pattern defect in a semiconductor wafer in a semiconductor inspection process.

[0002]

2. Description of the Related Art In a series of semiconductor manufacturing processes, a defect inspection step for determining whether or not a pattern formed on a wafer has a defect is provided. FIG. 7 is an explanatory diagram showing a defect inspection process. There are two methods for inspecting defects on a pattern on a wafer. One is to determine the presence / absence of a defect by comparing patterns at the same location of adjacent chips 1a, 1b, and 1c, as shown in the lower part of FIG. The other is to use a set of patterns 3a and 3b as a cell 2 as shown in the upper part of FIG.
Are compared with each other to determine the presence or absence of a defect. Particularly, in a memory product such as a DRAM or the like, since there are many repetitive patterns in a chip, inspection is often performed by this method.

FIG. 6 is an explanatory diagram of a pattern defect inspection step by comparing cells. In this pattern defect inspection process, the patterns 3a and 3b are scanned by the sensor 4 in order from the left, and images of the patterns 3a and 3b are captured. The scanned image is converted into a 256-level gray scale, and each pixel 5
Is plotted for each. In this manner, the same portions of the data 6a and 6b plotted in gray scale are superimposed. Then, by taking the difference between the superimposed portions in the above-mentioned 256 gray scales, the pattern 3
It is determined whether a or 3b has a defect. That is,
If there is no difference between the superimposed portions, the two patterns are the same, and in this case, it is considered normal. When there is a superposition difference 7, the two patterns are different, and at this time, it is determined that one of the patterns is abnormal. This inspection is performed in order from the left side in FIG. 6, and if a difference is detected twice, it is determined that the pattern has an abnormality. These results are recorded in the determination device, and when the inspection of all the inspection areas is completed, a map of the inspection area is created so that it is possible to determine where an abnormality has occurred.

[0004] However, depending on the wafer to be inspected, the wafer may be very bright because of its high reflectance, or may be very dark because of its low reflectance. In such a case, the brightness of the pattern is determined by the above-described 25
In some cases, the pattern goes out of the range of six gradations, the difference between the patterns to be inspected cannot be identified, and the defect cannot be determined.
Therefore, the light level, which is the reference of the brightness taken into the determination device, is adjusted so that the difference between the patterns to be inspected can be identified, and the defect of the pattern is determined. Conventionally, the brightness of the wafer is measured for each wafer to be inspected, and the light level is adjusted as described above. Conventionally, a worker selects an appropriate area from an inspection area in a chip, and sets a light level by trial and error using the brightness of the area as a reference value.

[0005]

However, the conventional method has the following problems. As described above, since the setting of the light level is arbitrarily determined by the operator through trial and error, the light level must be set for each process, which is very troublesome. Further, in which region the light level is to be set is determined by the operator, the obtained data has no reproducibility, and improvement has been desired in terms of objective comparison of data.

The semiconductor wafer according to the present invention has been made in order to solve the above-mentioned drawbacks of the prior art. Therefore, even if the type of wafer and the type of process are different, the write level can be accurately set and the write level can be set. An object of the present invention is to perform the setting in a predetermined area so that the obtained data has reproducibility and efficiently perform a defect inspection.

[0007]

In order to achieve the above object, in a semiconductor wafer according to the present invention, a plurality of pattern areas for a defect inspection step, which are areas having different reflectances, are provided in a predetermined area of the semiconductor wafer. It was configured to be formed. This allows you to set the light level accurately,
Objectivity can be given to the comparison with other inspection areas.

The reflectivity of the pattern area is set according to the density of the cut-out portions formed in the wafer. Therefore, a pattern can be created relatively easily.

The pattern is formed using the same material at the time of forming a chip pattern in a chip before the defect inspection process. Therefore, it is not necessary to separately provide a wafer forming process, and it is possible to collectively form the patterns in a chip.

Further, the pattern area is provided at the same position for each chip. For this reason, the search at the time of setting the light level can be easily performed.

[0011] Further, the pattern is formed of only linear portions. Thus, the reticle can be created relatively easily, and the pattern can be easily created.

The pattern does not include an isolated convex portion. For this reason, it is possible to reduce a possibility that the pattern is accidentally scattered to cause a product defect.

In each of the above-mentioned pattern areas, a pattern-penetrating portion having the same shape is arranged uniformly depending on the density. Thereby, the reflectance can be kept constant in the pattern area without being affected by the pattern arrangement.

In the defect inspection method for a semiconductor wafer according to the present invention, a light level is set based on the reflected light of the semiconductor wafer, and the same part of a chip pattern in a different chip or the same chip is read and a gray level in a predetermined stage is read. In a defect inspection process of a semiconductor wafer for determining the presence or absence of a pattern defect by converting to a scale and taking a gradation difference, in a semiconductor wafer defect inspection process, a plurality of different reflectance regions formed in a predetermined region of the semiconductor wafer are used. The light level is set. Further, the pattern of the pattern area is formed by using the same material at the time of forming a chip pattern in the chip at the stage prior to the defect inspection step, and the light level is set.

[0015]

Embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present embodiment, an inspection pattern for setting a light level for determining a reference of brightness to be compared in an inspection process by comparing cells will be described.

FIG. 1 is an explanatory diagram of semiconductor test pattern areas 20a to 20e in the embodiment of the present invention. In the present embodiment, semiconductor test pattern areas 20a to 20e are provided in the pattern area forming area 21a of the chip 22 to be tested. The semiconductor test pattern areas 20a to 20e are formed in the scribe line 24 below the chip 22 in FIG. 1 and have different reflectivities for predetermined test light. In the present embodiment, the reflectance of the pattern area 20a at the left end is 10%, and the reflectance increases by 20% toward the right. The reflectance of the pattern area 20e at the right end is 90%. It is empirically known that the reflectivity changes due to the density of the cut-out portions of the arranged patterns. In this embodiment, the reflectivity of the semiconductor inspection pattern areas 20a to 20e is changed by the cut-out portions 28.
Is adjusted by the density of Therefore, the reflectance can be adjusted more easily than by changing the pattern material in the pattern area. FIG. 2 is an enlarged view of the semiconductor test pattern areas 20a, 20c, and 20e in the present embodiment. 2A shows a semiconductor test pattern area 20a having a reflectance of 10%, FIG. 2B shows a semiconductor test pattern area 20c having a reflectance of 50%, and FIG. FIG. 5 is an enlarged view of a semiconductor inspection pattern area 20e. As can be seen from each of the figures, the pattern-penetrating portions 28 to be formed are denser in a pattern area having a low reflectance than in a pattern area having a high reflectance. The same applies to the other pattern areas 20b and 20d (not shown). The lower the reflectivity of the pattern area, the denser the cutout portion 28 to be formed. The pattern in the pattern areas 20a to 20e is provided with a square pattern hollow portion 28 having the same shape in each of the pattern areas 20a to 20e. Further, the pattern areas 20a to 20a
The pattern in 0e is formed only of the straight line portion. For this reason, it is relatively easy to create a reticle at the time of pattern creation, and a pattern can be easily created. In addition, since the pattern is connected to each other and there are no isolated convex portions, peeling and scattering of the pattern are less likely to occur, and the risk of causing a product defect can be reduced.

The semiconductor test pattern of the present embodiment is made of the same material as the chip pattern 27 of the chip 22 by incorporating it into the step of forming the chip pattern 27 of the chip 22 prior to the test process. That is, in the present embodiment, the chip pattern 27 of the chip 22 is made of a nitride film, and the semiconductor test patterns 29a to 29e are also made of a nitride film. FIG. 3 is a schematic explanatory diagram of a process of generating a semiconductor test pattern. As shown in FIG. 3A, when the chip pattern 27 of the nitride film is formed, the silicon substrate 3
0, a thin oxide film 25 is disposed thereon, and a nitride film 2
6 are formed. At this time, the nitride film 26 is also formed on the scribe line 24 in the same manner. And FIG.
The chip pattern 27 on the nitride film 26 as shown in FIG.
The mask 32 is arranged at the formation location, and at this time, the mask 33 is also arranged at the semiconductor inspection pattern 29 formation location on the scribe line 24. Then, after removing the nitride film 26 in a portion without the masks 32 and 33 by etching, the masks 32 and 33 are also removed, and a semiconductor test pattern 29 is formed on the scribe line 24 as shown in FIG. . For this reason, there is no need to newly provide a step of forming the semiconductor inspection pattern 29, and the chip pattern 2
7 according to the production process.

In the above configuration, the semiconductor inspection process is performed as follows. FIG. 4 is a flowchart showing a procedure of an inspection process based on a comparison between the cells 34. FIG. 5 is an explanatory diagram of an inspection process based on a comparison between the cells 34. First, one of the semiconductor inspection pattern areas 20a to 20e arranged on the scribe line 24, for example, the reflectance 10
The read level is set and the light level is set. Then, the chip patterns 27a and 27b in the pattern cells 34 on the chip 22 are sequentially scanned from the left. The scanned image is converted into 256 gray levels by a determination device (not shown). The decision device plots the gray level converted value for each pixel 38 to create an image 38. At this time, if the initially set light level is too dark and the defect cannot be recognized, the light level is taken in another semiconductor inspection pattern area 20b having a reflectance of, for example, 30%, and the comparative inspection is performed in the same manner as described above. . And the created image 40
The presence or absence of a defect is determined by superimposing a and 40b on each other and taking the gradation difference 42 of the image at a constant value. That is, if the tone difference 42 is, for example, 5 or more, the pattern cell 34 is defective, and if the tone difference 42 is less than 5, it is determined that there is no defect in the pattern cell 34, and the defective cell 27c is detected. . In the present embodiment, when this defect inspection is performed, it is possible to record in the determination device at what reflectance the light level has been set, so that other inspection areas in which similar patterns are arranged The criterion of the light level can be applied to the wafer and the wafer, and the defect inspection can be made objective. It can also be used for adjusting the light level of another determination device. That is, when the same wafer is measured by another determination device, an appropriate light level can be set.

Although the embodiment has been described in connection with the case where the defect inspection is performed for each cell, the present invention can also be used in the case where the defect inspection is performed for each chip. The shape of the pattern is not particularly limited as long as it is a combination of the same pattern.
Further, the pattern area is not limited to the scribe line area, but may be formed in the chip if it is an unused area. In the embodiment, the material of the pattern in the pattern area is a nitride film. However, the material of the pattern depends on the material of the chip pattern generated in the inspection area. For example, if the chip pattern is Al, the pattern is also Al. If the chip pattern is an oxide film, the pattern is also made of an oxide film. At that time, the pattern area is created, for example, in the pattern area 21b while being shifted in the pattern area creation area.

[0020]

As described above, in the semiconductor wafer of the present invention, a plurality of pattern areas having different reflectivities are provided for each inspection area.
By accurately setting the write level and providing the reproducibility of the write level data, the data can be used for another defect inspection, and the defect inspection can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a semiconductor pattern area according to an embodiment of the present invention.

FIG. 2 is a partially enlarged view of a semiconductor pattern area according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating generation of a semiconductor pattern area according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a defect inspection step according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of a conventional inspection method.

FIG. 6 is an explanatory diagram of a conventional defect inspection process.

FIG. 7 is a flowchart of a conventional defect inspection process.

[Explanation of symbols]

 1a-c chip 2 cell 3a pattern 3b pattern 4 sensor 5 pixel 6a data 6b data 7 difference 20a-e pattern area 21a-c pattern area formation area 22 chip 24 scribe line 25 oxide film 26 nitride film 27 chip pattern 27a chip pattern 27b Chip pattern 27c Defective cell 28 Pattern cut-out part 29 Semiconductor defect inspection pattern 29a-e Semiconductor defect inspection pattern 30 Silicon 32 Mask 33 Mask 34 Cell 36 Defective cell 38 Image 40 Image 40a Image 40b Image 42 Difference

Claims (9)

[Claims] 1. A semiconductor wafer, wherein a plurality of pattern areas for a defect inspection process, which are regions having different reflectances, are formed in a predetermined region of the semiconductor wafer. 2. The semiconductor wafer according to claim 1, wherein the reflectivity of the pattern area is set based on the density of a cut-out portion formed in the wafer. 3. The method according to claim 1, wherein the pattern is formed at a stage prior to a defect inspection step.
3. The semiconductor wafer according to claim 2, wherein the same material is used for forming a chip pattern in the chip. 4. The pattern area according to claim 1, wherein said pattern area is provided at the same position for each chip.
4. The semiconductor wafer according to any one of items 1 to 3, 5. The semiconductor wafer according to claim 2, wherein said pattern is formed only of a straight portion. 6. The semiconductor wafer according to claim 2, wherein the pattern does not include an isolated convex portion. 7. The semiconductor wafer according to claim 2, wherein in each of the pattern areas, pattern cutouts having the same shape are uniformly arranged according to density. 8. A light level is set based on reflected light from a semiconductor wafer, and the same part of a different chip or a chip pattern in the same chip is read and converted to a gray scale at a predetermined stage to obtain a difference in gradation. Thereby, in the defect inspection step of the semiconductor wafer for determining the presence or absence of a pattern defect, the write level is set by a pattern area which is a plurality of regions having different reflectances formed in a predetermined region of the semiconductor wafer. Semiconductor wafer defect inspection method. 9. The semiconductor according to claim 9, wherein a pattern in the pattern area is formed using the same material when a chip pattern is formed in a chip before a defect inspection step, and a write level is set. Wafer defect inspection method.